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* mpc52xx: Get rid of board-specific #ifdef's in cpu/mpc5xxx/ide.cGrzegorz Bernacki2009-03-18-1/+1
| | | | | | | | | | Total5200 and digsy MTC use I2C port 2 pins as a ATA chip select. To avoid adding board-specific ifdefs to cpu/mpc5xxx/ide.c new define CONFIG_SYS_ATA_CS_ON_I2C2 was introduced. It is used by Total5200 and will be used by digsy MTC and other boards with ATA CS on I2C pins. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* 8xx, icache: enabling ICache not before running from RAMHeiko Schocher2009-03-18-1/+1
| | | | | | | with the new CONFIG_SYS_DELAYED_ICACHE config option, ICache is not enabled before code runs from RAM. Signed-off-by: Heiko Schocher <hs@denx.de>
* ColdFire: PLATFORM_CPPFLAGS updates for new compilerTsiChung Liew2009-03-17-7/+7
| | | | | | | Update PLATFORM_CPPFLAGS to accept 4.3.x version of ColdFire compiler. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Fix M54451 serial boot dram setupTsiChung Liew2009-03-17-2/+2
| | | | | | | | The serial boot dram extended/standard mode register was not setup and was using default DRAM setup causing the U-boot was unstable to boot up in serial mode. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* Coldfire: XL Bus minor fixesarun c2009-03-17-3/+3
| | | | | | | According to coldfire manual data timeout > address time out also use correct macro to program XARB_CFG Signed-off-by: Arun C <arunedarath@mistralsolutions.com>
* Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-03-15-0/+1
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| * sh: Add netdev header fixing of warning/buildNobuhiro Iwamatsu2009-03-12-0/+1
| | | | | | | | | | Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-03-15-7/+11
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| * | mpc83xx: Add bank configuration to FSL spd_sdram.cJerry Van Baren2009-03-14-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | The routine assumed 4 bank SDRAMs, enhance to configure for 4 or 8 bank SDRAMs. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: correctly set encryption and I2C bus 0 clockNorbert van Bolhuis2009-03-14-1/+1
| |/ | | | | | | | | | | | | | | | | | | This patch makes sure the correct mask is applied when setting the encryption and I2C bus 0 clock in SCCR. Failing to do so may lead to ENCCM being 0 in which case I2C bus 0 won't function. Signed-off-by: Norbert van Bolhuis <nvbolhuis@aimvalley.nl> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-03-15-0/+26
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| * | OMAP3: Add support for OMAP3 die IDDirk Behme2009-03-13-0/+26
| |/ | | | | | | | | | | Read and store OMAP3 die ID in U-Boot environment. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-pxaWolfgang Denk2009-03-15-22/+24
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| * PXA: timer use do_div and simplify itJean-Christophe PLAGNIOL-VILLARD2009-03-09-22/+24
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Fix mpc85xx ddr-gen3 ddr_sdram_cfg.Ed Swarthout2009-03-09-2/+2
|/ | | | | | | Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-03-09-3/+75
|\ | | | | | | | | | | | | Conflicts: lib_ppc/board.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * 8360, kmeter1: added bootcount feature.Heiko Schocher2009-03-05-0/+52
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add CONFIG_BOOTCOUNT_LIMIT feature for 8360 CPU. The bootcounter uses 8 bytes from the muram, because no other memory was found on this CPU for the bootcount feature. So we must correct the muram size in DTS before booting Linux. This feature is actual only implemented for MPC8360, because not all 83xx CPU have qe, and therefore no muram, which this feature uses. Signed-off-by: Heiko Schocher <hs@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * 83xx: Fix some bugs in spd sdram codeDave Liu2009-03-05-3/+23
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. RD_TO_PRE missed to add the AL, and need min 2 clocks for tRTP according to DDR2 JEDEC spec. 2. WRTORD - tWTR need min 2 clocks according to DDR2 JEDEC spec. 3. add the support of DDR2-533,667,800 DIMMs 4. cpo 5. make the AL to min to gain better performance. The Micron MT9HTF6472CHY-667D1 DIMMs test passed on MPC837xEMDS platform at 266MHz/333MHz/400MHz data rate. items 1, 2 and 5: Acked-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Reported-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se> Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Moved SC520 Files (fix commit 407976185e0dda2c90e89027121a1071b9c77bfb)Graeme Russ2009-02-25-5/+53
|/ | | | | | Fixes commit 407976185e0dda2c90e89027121a1071b9c77bfb Signed-off-by: Graeme Russ <graeme.russ at gmail.com>
* mpc83xx: PCI: Fix hard-coded first_busno valueAnton Vorontsov2009-02-23-1/+1
| | | | | | | | | | | | | | | | | | | | | We should use pci_last_busno() in pci_init_bus(), otherwise we'll erroneously re-use PCI0's first_busno for PCI1 hoses. NOTE: The patch is untested. All MPC83xx FSL boards I have have PCI1 in miniPCI form, for which I don't have any cards handy. But looking in cpu/mpc85xx/pci.c: ... #ifdef CONFIG_MPC85XX_PCI2 hose = &pci_hose[1]; hose->first_busno = pci_hose[0].last_busno + 1; And considering that we do the same for MPC83xx PCI-E support, I think this patch is correct. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: PCI: Fix bus-range fdt fixups for PCI1 controllersAnton Vorontsov2009-02-23-2/+2
| | | | | | | | | | | This patch fixes copy-paste issue: pci_hose[0]'s first and last busnos were used to fixup pci1's nodes. We don't see this bug triggering only because Linux reenumerate buses anyway. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: PCIe: Fix CONFIG_PCI_SCAN_SHOW reporting bogus valuesAnton Vorontsov2009-02-23-2/+7
| | | | | | | | | This patch fixes an issue in config space read accessors: we should fill-in the value even if we fail (e.g. skipping devices), otherwise CONFIG_PCI_SCAN_SHOW reports bogus values during boot up. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: PCIe: Don't start bus enumeration at 0Anton Vorontsov2009-02-23-3/+1
| | | | | | | | | | | | | | | | | | | Currently we assign first_busno = 0 for the first PCIe hose, but this scheme won't work if we have ordinary PCI hose already registered (its first_busno value is 0 too). The old code worked fine only because we have PCI disabled on MPC837XEMDS boards in stand-alone mode (see commit 00f7bbae92e3b13f2b3 "mpc83xx: fix PCI scan hang on the standalone MPC837xE-MDS boards"). But on MPC837XERDB boards we have PCI and PCIe, so the bug actually triggers. So, to fix the issue, we should use pci_last_busno() + 1 for the first_busno (i.e. last available busno). Reported-by: Huang Changming <Chang-Ming.Huang@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-02-22-2/+29
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| * OMAP3: Add OMAP3 auto detectionDirk Behme2009-02-22-2/+29
| | | | | | | | | | | | | | | | This patch adds OMAP3 cpu type auto detection based on OMAP3 register and removes hardcoded values. Signed-off-by: Steve Sakoman <sakoman@gmail.com> Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* | Blackfin: disable syscontrol code for nowMike Frysinger2009-02-21-0/+1
|/ | | | | | | | | | Looks like the initcode updates fell out of order during my merges. The patch that really fixes up this code is part of power-on overhaul and so is too large for merging at this point. Instead, we can disable the code as no currently in-tree board depends on it. The next merge window will fix things up properly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* MIPS: cpu/mips/Makefile: Add a missing START lineShinya Kuribayashi2009-02-21-0/+1
| | | | | | | | In the commit 79b51ff8205f0354d5300570614c1d2db499679c ([MIPS] cpu/mips/ Makefile: Split [CS]OBJS onto separate lines), I wrongly deleted a START line. This patch puts it back. Signed-off-by: Shinya Kuribayashi <shinya.kuribayashi@necel.com>
* pxa: move mmc drivers to drivers/mmcJean-Christophe PLAGNIOL-VILLARD2009-02-20-789/+1
| | | | | | introduce new macro CONFIG_PXA_MMC to activate it Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ARM:PXA Remove redefinition of mmc_cid and mmc_csd.Tom Rix2009-02-20-51/+0
| | | | | | These structures are defined in the common mmc.h This was compile checked on cerf250.
* pxa: fixing get_timer to return time in miliseconds.Micha Kalfon2009-02-20-7/+18
| | | | | | | | Fixing the get_timer function to return time in miliseconds instead of ticks. Also fixed PXA boards to use the conventional value of 1000 for CONFIG_SYS_HZ. Signed-off-by: Micha Kalfon <smichak.uv@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-02-19-2/+2
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| * ppc4xx: PCIe: Change 16GB inbound memory to 4GBStefan Roese2009-02-18-2/+2
| | | | | | | | | | | | | | This patch fixes a problem recently seen on some 4xx platforms. For example on Kilauea PCIe slot #0. Signed-off-by: Stefan Roese <sr@denx.de>
* | Coding style cleanup, update CHANGELOGWolfgang Denk2009-02-19-1/+2
|/ | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 83xx: Add eSDHC support on 8379 EMDS boardAndy Fleming2009-02-16-0/+14
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add eSDHC support for 8536 DSAndy Fleming2009-02-16-0/+15
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* Eliminated arch-specific mmc header requirementAndy Fleming2009-02-16-0/+191
| | | | | | | | | | The current MMC infrastructure relies on the existence of an arch-specific header file. This isn't necessary, and a couple drivers were forced to implement dummy files to meet this requirement. Instead, we move the stuff in those header files into a more appropriate place, and eliminate the stubs and the #include of asm/arch/mmc.h Signed-off-by: Andy Fleming <afleming@freescale.com>
* Convert mmc_init to mmc_legacy_initAndy Fleming2009-02-16-3/+3
| | | | | | This is to get it out of the way of incoming MMC framework Signed-off-by: Andy Fleming <afleming@freescale.com>
* Eliminate support for using MMC as memoryAndy Fleming2009-02-16-40/+0
| | | | | | MMC cards are not memory, so we stop treating them that way. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 32bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b108122009-02-16-1/+8
| | | | | | | This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
* 86xx: Update CPU info output on bootupPeter Tyser2009-02-16-41/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 86xx: Reset updatePeter Tyser2009-02-16-61/+19
| | | | | | | | | | Update the 86xx reset sequence to try executing a board-specific reset function. If the board-specific reset is not implemented or does not succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard reset procedure than the previous method and allows all board peripherals to be reset if needed. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* fsl-ddr: Allow system to boot if we have more than 4G of memoryKumar Gala2009-02-16-1/+1
| | | | | | | | | | Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report an error and hang. Instead of doing that since DDR is mapped in the lowest priority LAWs we setup the DDR controller and the max amount of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED) Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
* mpc85xx: Add support for the P2020Srikanth Srinivasan2009-02-16-0/+3
| | | | | | | | | | | Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-47/+27
| | | | | | | | | Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala2009-02-16-0/+4
| | | | | | | | If we only have one controller we can completely ignore how memctl_intlv_ctl is set. Otherwise other levels of code get confused and think we have twice as much memory. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Format cpu freq printing to handle 8 coresKumar Gala2009-02-16-3/+5
| | | | | | | Only print 4 cpu freq per line. This way when we have 8 cores its a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Fix initialization of the SDRAM_CODT registerCarolyn Smith2009-02-12-5/+2
| | | | | | | | | This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2 initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits. Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Autocalibration can set RDCC to over aggressive value.Adam Graham2009-02-12-29/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanup; update CHANGELOGWolfgang Denk2009-02-12-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 8xx serial, smc: Coding-Style cleanup serial SMC driverHeiko Schocher2009-02-11-48/+24
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
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