summaryrefslogtreecommitdiff
path: root/cpu
Commit message (Collapse)AuthorAgeLines
* ENGR00170837 [MX6]Add temperatuer check into ubootAnson Huang2011-12-22-0/+103
| | | | | | | | | We need to check CPU temperature in uboot, if cpu is too hot, we will let it waiting there until cpu temperature drop to save region, then go on boot up. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00162642: Fix bug in setting VDDSOC voltageRanjani Vaidyanathan2011-12-20-2/+2
| | | | | | Fix incorrect VDDSOC voltage setting in uboot. Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00160621 [MX6]Workaround for reset issueAnson Huang2011-12-20-0/+25
| | | | | | | | | | | | | | | | | | | Add workaround for POR/wdog reset issue, we need to do a CORE LDO reset everytime POR/wdog reset, otherwise kernel will crash or hang when we booting more than 2 cores. Root cause is still under investigation, it is analog/power related issue, may take long time to identify the root cause, we need to add workaround to make function ready first. The flow of workaround is as below: 1. Check CORE LDO reset flag, currently stored in SNVS_LPGPR[0]; 2. If it is there, clear it, go on boot up system; If not, Set the flag, configure wdog to timeout in 0.5 seconds, then disable CORE LDO and wait for wdog timeout; This workaround will bring 0.5~1 seconds delay of booting. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00170299-1 Android: add support fastboot functionZhang Jiejing2011-12-15-1/+71
| | | | | | add support for otg in MX6Q uboot to enable fastboot function. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00163513 MX6Q-UBOOT : Add download_mode cmdEric Sun2011-11-30-0/+50
| | | | | | | | | | | | | Add "download_mode" command to U-Boot. It will force a system reset and let boot running in "boot from serial rom" mode, which can be used by manufacturing tool. The command will triggle a write to SRC_GPR9 and SRC_GPR10, then triggle a watchdog reset. GPR9 and GPR10 can maintain their value during the reset, the value in it make ROM to start in "boot from serial rom" mode. After that GPR9 and GPR10 are written by their original value for normal boot. Signed-off-by: Eric Sun <jian.sun@freescale.com>
* ENGR00162938 MX5: Add download_mode command in uboot to enter MFG download mode.Zhang Jiejing2011-11-23-0/+39
| | | | | | | | | | | | Add download_mode command in uboot to enter MFG dowload mode , you can try download mode command in uboot and enter download mode. it first set srtc register, then before enter linux, it will clear these register to prevent the up comming watchdog reset will enter mfgtool mode. only add mx53 now. Signed-off-by: Zhang Jiejing <jiejing.zhang@freescale.com>
* ENGR00162874: Add enet clk change support for mx6Terry Lv2011-11-23-7/+75
| | | | | | Add enet clk change support for mx6. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00162570: MX6-Increase VDDSOC_CAP voltage to 1.2VRanjani Vaidyanathan2011-11-17-0/+7
| | | | | | | | Set the VDDSOC LDO to increase the VDDSOC cap to 1.2V. This is required for correct functioning of GPU and when the ARM LDO is set to 1.225V (when ARM core is at 1GHz). Signed-off-by: Ranjani Vaidyanathan <ra5478@freescale.com>
* ENGR00161373 Move the MAC address read from fuse code to MX6 SoC fileMahesh Mahadevan2011-11-03-2/+21
| | | | | | | Move the code to read the mac address from the fuse to SoC file and out of the board file Signed-off-by: Mahesh Mahadevan <r9aadq@freescale.com>
* ENGR00161254 MX6Q: Add NAND support in UbootAllen Xu2011-11-03-1/+3
| | | | | | | | Add iomux and clock setting in Uboot code to support NAND, due to the conflict between NAND and SD, NAND function is not enabled in default configuration. Signed-off-by: Allen Xu <allen.xu@freescale.com>
* ENGR00139215 iMX61 Uboot support blow fuseRyan QIAN2011-11-02-0/+24
| | | | | | | | 1. add force option to blow operation 2. add blown value check 3. add simple validation for zeros returned by 'simple_strtoul' call Signed-off-by: Ryan QIAN <b32804@freescale.com>
* ENGR00139254: Enable MX6Q Uboot Splash ScreenSandor Yu2011-09-02-0/+7
| | | | | | | | | | | | | | Only support LVDS0 splash screen. Enable splash process: 1.define CONFIG_SPLASH_SCREEN in mx6q_sabreauto.h 2.Config U-boot with followed command:() setenv splashimage '0x30000000' #Set splash position as Center setenv splashpos 'm,m' #Set LVDS via LVDS bridge 0 setenv lvds_num 0 Signed-off-by: Sandor Yu <r01008@freescale.com>
* ENGR00155283: Set dpgdck0_2_en to 0 when freq is lower than 300MHzTerry Lv2011-09-01-2/+4
| | | | | | | | 1. Set dpgdck0_2_en to 0 when required freq is lower than 300Mhz. 2. When dpgdck0_2_en is 0, the formula to calculate output freq will be changed to 2 * freq * []. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00155156 [MX6]Clean up debug info in ubootAnson Huang2011-08-22-23/+0
| | | | | | | | 1. ENET don't need to enable ENET pll clock; 2. Enable cpu debug clock in case of using JTAG; 3. Clean up some debug info during bring up. Signed-off-by: Anson Huang <b20788@freescale.com>
* ENGR00151310 mx53 smd: force warm reset as cold resetLily Zhang2011-07-22-15/+0
| | | | | | | | | | This patch is used to support watchdog timeout in SMD RevA, RevB board. 1. Revert "ENGR00143469 mx53 smd: pull down GPIO_9 to reset the board". 2. Force warm reset as cold reset. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00144424 MX6: enable uboot for ARM2(SABREAUTO) CPU boardAnson Huang2011-06-24-0/+1662
| | | | | | | | | | | | | Use 528M DDR script Disable L2 cache because rom enable L2 cache when use plug-in Fix usdhc pad settings Remove mac address hardcode Signed-off-by: Anson Huang <b20788@freescale.com> Signed-off-by: Richard Zhu <r65037@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00143298: Reinit uart after using clk commandTerry Lv2011-05-20-0/+6
| | | | | | | For clk command always make console output mess characters, here we reinitilize it after clock is changed. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00143469 mx53 smd: pull down GPIO_9 to reset the boardLily Zhang2011-05-16-0/+15
| | | | | | | | | In mx53 smd, to type "reset" command in u-boot console can not reset the system. It hangs in ROM with unknown reason. This patch adds one workaround to configure GPIO_9 (WDT_OUTPUT_B) as GPIO and pull down it to reset DA9053 PMIC. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00141885: mx50 and mx53 reboot fail when booting from spi norTerry Lv2011-04-20-2/+15
| | | | | | | mx50 reboot fail when booting from spi nor. Reconfigure eCSPI SS signal as GPIO before reset. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141335-2: get more accurate ipg_per clock frequencyTerry Lv2011-04-11-17/+24
| | | | | | | Add perclk_lp_apm_sel check to function __get_ipg_per_clk. This will get more accute clock frequency. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00141556: Fix copyright issueTerry Lv2011-04-08-2/+4
| | | | | | | | | | | We're following the following rules: 1. FSL copyright should be added for freescale added and modified files. 2. FSL copyright should go after existing copyrights. 3. For Duplicate FSL copyright, Our copyright will go after that also. 4. FSL copyright should not include personal names as part. 5. For only FSL copyright, "All rights reserved" is not mattered. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00140824 Android: Enable fastboot support for mx50 rdpSammy He2011-03-21-3/+62
| | | | | | Enable fastboot support for mx50 rdp. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00140767: Improve mx5x DDR clock functionTerry2011-03-17-47/+41
| | | | | | | | | | | | | | As now mx51 DDR frequency is derived from PLL1. We need to get DDR frequency from PLL1. Mx53 don't use PLL1 for ddr clock source, so just the precision is adjusted. Mx50 don't support clk command yet. DDR config function is modified according to mx50 spec, but not tested yet. Signed-off-by: Terry <r65388@freescale.com>
* ENGR00138468-1 MX5 video:Disable DP/DC/DI/IDMAC before go to kernelLiu Ying2011-01-25-0/+8
| | | | | | | This patch fixes the kernel bootup random hang issue by disabling DP/DC/DI/IDMAC before we go to kernel. This is a workaround. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137894-2 MX53: Add ipu base addr and ipu clockLiu Ying2011-01-13-0/+43
| | | | | | This patch adds ipu base address and ipu clock. Signed-off-by: Liu Ying <Ying.Liu@freescale.com>
* ENGR00137604: Change PLL4 to 455MHz for mx53Terry Lv2011-01-07-1/+4
| | | | | | | Required by display to set ldb. We need to set PLL4 to 455MHz. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00137372 MX53: Switch back to use DCD and update DDR scriptsLily Zhang2010-12-28-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 1. This patch is used to switch back to use DCD for flash header instead of plug-in. This change request is due to the following reasons: 1) U-boot community doesn't accept current plug-in solution when upstreaming. 2) Plug-in isn't supported by MX53 ROM serial download mode. No effective workaround is found now. To use the same code base to support normal U-Boot and MFG tool better, adopt DCD solution firstly. 3) Current MX53 DDR scripts don't exceed the length limitation of DCD. For MX53 TO2.0 EVK/ARM2 board, raise DDR frequency to 400MHZ after VCC and VDDA voltages are raised as 1.3V. Since ARM2 CPU2 board share the same script with EVK, delete ARM2 CPU2 config files. ARM2 CPU2 board can share the same bootloader with EVK. 2. Update MX53 DDR2 scripts for TO1.0/TO2.0 EVK/ARD/ARM2 boards The script "MX53_TO2_DDR2_EVK_ARD.inc" is located under http://compass.freescale.net/livelink/livelink? func=ll&objId=221058910&objAction=browse&viewType=1 This script is published by ATX and FIL team on Dec 16th, 2010 3. Update MX53 ARM2 CPU3 DDR3 script "MX53_TO2_DDR3_CPU3.inc" under the same compass folder Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00134068 MX51 BBG:Support CLAA WVGA splashimageLiu Ying2010-12-16-0/+43
| | | | | | | | | | | 1) IOMUX/backlight support for CLAA WVGA LCD panel. 2) Add video mode for CLAA WVGA LCD panel. 3) Support IPU di1 interface for framebuffer. 4) Enhance IPU driver. 5) Add freescale 600x400 8BPP BMP logo. Signed-off-by: Terry Lv <R65388@freescale.com> Signed-off-by: Liu Ying <b17645@freescale.com>
* ENGR00133727: uart outputs messy code when kernel starts on mx51Terry Lv2010-12-14-0/+69
| | | | | | | uart outputs messy code when kernel starts on mx51. Change uart clock to use pll2 as source clock. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00134098-2 MX53: Add fastboot support for android.Sammy He2010-11-26-0/+51
| | | | | | Add fastboot support for mx53 EVK android. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00134098-1 MX51: Update fastboot usb init seqSammy He2010-11-26-6/+8
| | | | | | Update fastboot usb init seq, and use defined macro for coding. Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00133551-1 Add freescale usb udc support for i.mx51 platform.Sammy He2010-11-18-0/+52
| | | | | | | Add imx_udc for usb gadget on i.mx51 platform. Signed-off-by: Hu Hui <b29976@freescale.com> Signed-off-by: Sammy He <r62914@freescale.com>
* ENGR00132909 MX53 Uboot: Support for TO2Anish Trivedi2010-11-15-7/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Support new DDR script entitled "Rita_TO2_init_DDR2_CPU2_CMOS_TEST_CAL_v1.inc" for DDR2 boards including MX53 EVK, ARD, and ARM2 CPU2. These new settings did not apply to TO1. Therefore, changed the DCD for these boards to a plugin so that TO1 and TO2 can both be supported using conditional execution of new DDR settings. During bootup on TO2, DDR frequency is required to be below 400 MHz. Therefore, BOOT_CFG2[4] must be set to enable DDR at 333 MHz in ROM on all boards. Uboot determines silicon version and for TO2 boosts the VCC and VDDA voltages to 1.3V, after which the DDR frequency is also increased to 400 MHz. This requirement meant that uboot does not calibrate PLL2 anymore until the voltage is increased. Removed the calibration from lowlevel_init.S and from all mx53 include/configs files. Also required that during config_periph_clk(), only CBCMR register is touched to set source PLL. Other changes to CBCDR were removed. Switching to PLL2 bypass clk during reprogram was also removed. All these changes are required to increase DDR frequency to 400 MHz. DDR2 CPU2 board with TO1 requires the following hw cfgs: JP3 populated, and J8 set to 2-3. For DDR2 CPU2 board with TO2, both these jumpers should be depopulated. ARM2 CPU3 (with DDR3) DDR configurations were not changed. TO1 and TO2 can run well using existing DDR3 script. However, DCD was converted to plugin to align with other boards. Signed-off-by: Anish Trivedi <anish@freescale.com>
* ENGR00133049 Support nand flash for MX28Frank Li2010-11-04-1/+43
| | | | | | | Support nand basic read/write in MX28 u-boot. Signed-off-by: Frank Li <frank.li@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00132759 MX53: use 32K CLK as GPT sourceLily Zhang2010-10-19-38/+33
| | | | | | | | | | | | | MT29F16G08MAA NAND flash was failed on MX53 ARD/RevB board, but it's fine in RevA board. After check, it's found that udelay is not accurate on MX53 ARD/RevB board because GPT uses IPG peripheral clock and assume it is 50MHZ. However IPG peripheral clock is not 50MHZ in MX53 ARD/RevB board. So it causes udelay is not accurate. This patch changes GPT clk source as 32K to make udelay accurate. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132758 correct NFC_CLK definitionLily Zhang2010-10-19-1/+4
| | | | | | | | This patch is used to fix the issue caused by ENGR00132709. NFC_CLK definition should be used in cmd_clk interface. MXC_NFC_CLK should be used as internal clock name. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132709 MX53: add "clk nfc" command supportLily Zhang2010-10-18-0/+27
| | | | | | | | Add "clk nfc" command support. Limit NFC MAX clock as 34MHZ to be compatible with some old NAND flashes. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00132617 MX53: add NAND supportLily Zhang2010-10-17-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | Add NAND support for MX53 EVK and ARD. Need to use kobs-ng to flash U-Boot on MX53 TO1. Because MX51 TO1 ROM doesn't support bi swap solution and kernel enable bi swap, Must enable "ignore bad block" option when flashing U-Boot. The step is as following: echo 1 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad kobs-ng init --chip_0_device_path=/dev/mtd2 u-boot.bin echo 0 > /sys/devices/platform/mxc_nandv2_flash.0/ignorebad Since default configuration stores environment into SD card and U-Boot uses get_mmc_env_devno (Read SBMR register) to get MMC/SD slot information, you must insert SD card to bottom SD slot to get/store environment if you are using NAND boot on MX53 EVK. You must config boot dip setting well when doing NAND boot. For example, if you are using NAND 29F32G080AA NAND chip on MX53 EVK, you can set boot dips as the following for NAND boot: SW3: dip 7, 8 on; SW2: dip 3,5 on; SW1: dip 4,7,8 on. Other dips are off. Signed-off-by: Lily Zhang <r58066@freescale.com>
* ENGR00131779: Use serial_mxc as uart driver for all platformsTerry Lv2010-09-21-675/+18
| | | | | | Use serial_mxc as uart driver for all platforms. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00127167: Add gpmi nfc and apbh dma support for mx50.Terry Lv2010-09-19-228/+161
| | | | | | Add gpmi nfc and apbh dma support for mx50. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00126079: Add clk command support for mx51Terry Lv2010-08-11-6/+657
| | | | | | Add clk command support for mx51. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00125237: Fix incorrect copyright info.Terry Lv2010-08-04-11/+20
| | | | | | Fix incorrect copyright info. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00123924: Reconstructure fuse files and add fuse to mx53.Terry Lv2010-07-16-455/+0
| | | | | | | | | | 1. Reconstructure fuse. Move fuse files to common directory. 2. Read mac from fuse in fec. 3. Remove scc and srk command from fuse command. 4. Change fuse to iim. 5. Add fuse for mx53. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00124359 Add uboot support for MX50Jason Liu2010-07-07-0/+2286
| | | | | | | | | | | | | | Add initial support for MX50 -Support mddr200Mhz, lpddr2266Mhz ARM2 board, -Support boot from SD/MMC, -Support boot from SPI-NOR, -Support FEC, UART, -Support SD/MMC/SPI command within UBOOT Signed-off-by: Anish Trivedi <anish@freescale.com> Signed-off-by: Terry Lv <r65388@freescale.com> Signed-off-by: Jason Liu <r64343@freescale.com>
* ENGR00122651: Add dwc_ahsata supportTerry Lv2010-06-24-0/+2
| | | | | | Add dwc_ahsata support. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00123484 mx28:support saving environment into sd1Aisheng.Dong2010-06-08-15/+0
| | | | | | | | | Original uboot did not support sd1 and can only save environment into sd0 even actually you're booting from sd1. This patch adds the capability of saving environment into sd1 when you're booting from sd1. Signed-off-by: Aisheng.Dong <b29396@freescale.com>
* ENGR00123870 MX53: Set AXI_B clock to 200MhzJason Liu2010-05-26-7/+3
| | | | | | | | The clock for axi_b is set to 100Mhz which will cause IPU module has insufficient clock rate. This patch will increase axi_b clock to 200M and keep it not change when do clk config in uboot Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00123630 Set ddr clk clock according to the board IDrel_imx_2.6.31_10.05.02imx_v2009.08_10.05.02Jason Liu2010-05-19-22/+7
| | | | | | | | | | Set DDR clock to 400Mhz on MX53-EVK with DDR2 1GByte RevB Set DDR clock to 300Mhz on MX53-EVK with DDR2 2GByte RevA1 Remove the clock dump during boot, user can use clk command to get the clock information. Using help clk to get the command help Signed-off-by:Jason Liu <r64343@freescale.com>
* ENGR00123418: Add peripheral clock setup supportTerry Lv2010-05-14-66/+283
| | | | | | Add peripheral clock setup support. Signed-off-by: Terry Lv <r65388@freescale.com>
* ENGR00123278: Support clock operation functionsTerry Lv2010-05-11-2/+334
| | | | | | Support clock operation functions. Signed-off-by: Terry Lv <r65388@freescale.com>
generated by cgit v1.1 at 2024-12-29 17:11:30 +0000