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* Cleanup compiler warnings.Jon Loeliger2006-08-22-13/+10
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* Copy Global Data Pointer to r29 for DECLARE_GLOBAL_DATA_PTRHaiying Wang2006-08-17-1/+2
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* Fix caslat calculationJohn Traill2006-08-09-96/+39
| | | | Signed-off-by: John Traill <john.traill@freescale.com>
* Convert to mac-address in ethernet nodes.Jon Loeliger2006-08-09-4/+4
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* Move get_board_sys_clk to board directoryHaiying Wang2006-07-31-66/+0
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* Fix 8641HPCN pollutionJohn Traill2006-07-28-0/+2
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* Enable PCIE1 for MPC8641HPCN boardJin Zhengxiong-R641882006-06-27-110/+284
| | | | Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* Do not enable address translation on secondary CPUs.Jon Loeliger2006-06-15-15/+0
| | | | | | Do not set up BATs on secondary CPUs. Let Linux do the nasty. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Fix a get_board_sys_clk() use-before-def warning.Jon Loeliger2006-06-07-64/+64
| | | | Signed-off-by: Jon Loeliger <jdl@jdl.com>
* Review cleanups.Jon Loeliger2006-05-31-99/+37
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* White space cleanup.Jon Loeliger2006-05-31-14/+13
| | | | | | | | | Some 80-column cleanups. Convert printf() to puts() where possible. Use #include "spd_sdram.h" as needed. Enhanced reset command usage message a bit. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Moved mpc8641hpcn_board_reset() out of cpu/ into board/.Jon Loeliger2006-05-31-84/+6
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Remove dead debug code.Jon Loeliger2006-05-31-24/+0
| | | | Signed-off-by: Jon Loeliger <jdl@jdl.com>
* Move mpc86xx PIXIS code to board directoryJon Loeliger2006-05-31-293/+15
| | | | | | | | First cut at moving the PIXIS platform code out of the 86xx cpu directory and into board/mpc8641hpcn where it belongs. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Improve "reset" command's interaction with watchdog.Haiying Wang2006-05-30-5/+32
| | | | | | | | "reset altbank" will reset another bank WITHOUT watch dog timer enabled "reset altbank wd" will reset another bank WITH watch dog enabled "diswd" will disable watch dog after u-boot boots up successfully Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Fix two SDRAM setup bugs.Haiying Wang2006-05-30-7/+7
| | | | | | | Fix ECC setup bug. Enable 1T/2T based on number of DIMMs present. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Change arbitration to round-robin for SMP linux.Jon Loeliger2006-05-19-6/+9
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* Enable dual DDR controllers and interleaving.Jon Loeliger2006-05-19-121/+494
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* Remove L2 Cache invalidate polling.Jon Loeliger2006-05-19-11/+17
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* Remove unneeded INIT_RAM_LOCK cache twiddling.Haiying Wang2006-05-10-2/+3
| | | | | | Correctly tracks r29 as global data pointer now. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Cleanup whitespaces and style issues.Jon Loeliger2006-04-27-411/+339
| | | | | | | Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft.
* Initial support for MPC8641 HPCN board.Jon Loeliger2006-04-26-0/+4699
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* MPC5200: enable snooping of DMA transactions on XLB even if no PCIWolfgang Denk2006-04-18-4/+4
| | | | | is configured; othrwise DMA accesses aren't cache coherent which causes for example USB to fail.
* Some code cleanupWolfgang Denk2006-04-16-111/+111
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* Fix Lite500B support: Merge with /home/raj/git/u-boot.l5200b_pciWolfgang Denk2006-04-06-5/+5
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| * Set SDelay register in the DDR controller for the MPC5200B chip.Rafal Jaworowski2006-03-29-5/+5
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* | Merge with /home/sr/git/u-boot/4xx-sdramWolfgang Denk2006-04-05-34/+342
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| * | Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440)Stefan Roese2006-03-31-34/+342
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 405 SDRAM: - The SDRAM parameters can now be defined in the board config file and the 405 SDRAM controller values will be calculated upon bootup (see PPChameleonEVB). When those settings are not defined in the board config file, the register setup will be as it is now, so this implementation should not break any current design using this code. Thanks to Andrea Marson from DAVE for this patch. 440 DDR: - Added function sdram_tr1_set to auto calculate the TR1 value for the DDR. - Added ECC support (see p3p440). Patch by Stefan Roese, 17 Mar 2006
* | Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.SWolfgang Denk2006-04-03-1/+2
| | | | | | | | Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473]
* | GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk2006-03-31-233/+195
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* | Merge with http://www.denx.de/git/u-boot.gitMarkus Klotzbuecher2006-03-24-453/+4384
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| * Add support for MPC859/866 Rev. A.0Wolfgang Denk2006-03-18-3/+8
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| * Support for DDR with 32-data path. Addotional notes on injectingRafal Jaworowski2006-03-16-12/+49
| | | | | | | | multiple-bit errors.
| * Add support for ECC DDR initialization on MPC83xx.Marian Balakowicz2006-03-14-22/+108
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| * Add DMA support for MPC83xx.Marian Balakowicz2006-03-14-0/+85
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| * Add sync in do_reset() routine for MPC83xx after RPR registerMarian Balakowicz2006-03-14-0/+2
| | | | | | | | | | was written to. It is need on some targets when BAT translation is enabled.
| * Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx.Marian Balakowicz2006-03-14-0/+34
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| * Correct shift offsets in icache_status and dcache_status for MPC83xx.Marian Balakowicz2006-03-14-2/+2
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| * Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer andWolfgang Denk2006-03-13-167/+531
| | | | | | | | | | cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories Patch by Andreas Engel, 13 Mar 2006
| * Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.cStefan Roese2006-03-13-1/+1
| | | | | | | | Patch by Stefan Roese, 13 Mar 2006
| * cpu/ppc4xx/start.S : exceptions are enabled after relocationStefan Roese2006-03-13-23/+18
| | | | | | | | Patch by Cedric Vincent, 6 June 2005
| * au1x00_eth.c: check malloc return value and abort if it failedWolfgang Denk2006-03-13-2/+6
| | | | | | | | Patch by Andrew Dyer, 26 Jul 2005
| * Fix bug in [id]cache_status commands for MPC85xx processors;Wolfgang Denk2006-03-13-2/+2
| | | | | | | | | | | | should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
| * Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#mpc83xxWolfgang Denk2006-03-12-209/+349
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| | * Enable address translation on MPC83xxKumar Gala2006-02-10-179/+298
| | | | | | | | | | | | Patch by Kumar Gala, 10 Feb 2006
| | * Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xxKumar Gala2006-01-25-28/+21
| | | | | | | | | | | | Patch by Kumar Gala, 25 Jan 2006
| | * Only disable the MPC83xx watchdog if its enabled out of reset.Kumar Gala2006-01-11-0/+6
| | | | | | | | | | | | | | | If its disabled out of reset SW can later enable it if so desired Patch by Kumar Gala, 11 Jan 2006
| | * Allow config of GPIO direction & data registers at boot on 83xxKumar Gala2006-01-11-0/+8
| | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
| | * Enable time handling on 83xxKumar Gala2006-01-11-0/+10
| | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
| | * Make System IO Config Registers board configurable on MPC83xxKumar Gala2006-01-11-2/+6
| | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006
generated by cgit v1.1 at 2024-12-18 13:16:39 +0000