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* mpc85xx: Add support for the MPC8536Kumar Gala2008-08-27-1/+199
| | | | | | | | | | | The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-2/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Remove old SPD support from cpu/mpc85xxKumar Gala2008-08-27-1166/+0
| | | | | | | All 85xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add 85xx specific register settingKumar Gala2008-08-27-0/+318
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add e500 TLB helper for DDR codeKumar Gala2008-08-27-0/+64
| | | | | | | Provide a helper function that board code can call to map TLBs when setting up DDR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Remove old SPD support from cpu/mpc86xxKumar Gala2008-08-27-1352/+0
| | | | | | | All 86xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add 86xx specific register settingKumar Gala2008-08-27-0/+92
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add DDR2 DIMM paramter supportKumar Gala2008-08-27-0/+339
| | | | | | | | Compute DIMM parameters based upon the SPD information. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add DDR1 DIMM paramter supportKumar Gala2008-08-27-0/+343
| | | | | | | | Compute DIMM parameters based upon the SPD information in spd. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-2/+2432
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: add PCISLAVE support to 83XX_GENERIC_PCI setup codeIra W. Snyder2008-08-25-0/+26
| | | | | | | | | This adds a helper function to unlock the PCI configuration bit, so that any extra PCI setup (such as outbound windows, etc.) can be done after using the 83XX_GENERIC_PCI code to set up the PCI bus. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Minor coding style cleanup, updte CHANGELOGWolfgang Denk2008-08-25-7/+7
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MX31: fix bit masks in function mx31_decode_pll()Jens Gehrlein2008-08-25-2/+2
| | | | | | Bits MPCTL[MFN] and MPCTL[MFD] were not fully covered. Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
* Correct ARM Versatile Timer InitializationGururaja Hebbar K R2008-08-25-4/+35
| | | | | | | | | | | | | | | - According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271), -- Timer Value Register @ TIMER Base + 4 is Read-only. -- Prescale Value (Bits 3-2 of TIMER Control register) can only be one of 00,01,10. 11 is undefined. -- CFG_HZ for Versatile board is set to #define CFG_HZ (1000000 / 256) So Prescale bits is set to indicate - 8 Stages of Prescale, Clock divided by 256 - The Timer Control Register has one Undefined/Shouldn't Use Bit So we should do read/modify/write Operation Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
* ARM DaVinci: Removed redundant NAND initialization code.Hugo Villeneuve2008-08-25-2/+1
| | | | | | ARM DaVinci: Removed redundant NAND initialization code. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
* ARM DaVinci: Fix compilation error with new MTD code.Hugo Villeneuve2008-08-25-2/+0
| | | | | | ARM DaVinci: Fix compilation error with new MTD code. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
* ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fixTirumala R Marri2008-08-22-5/+5
| | | | | | | | | | | During recent PCI-E tests it has been found that current driverl level and de-emphasis values are not set correctly. After sweeping throgh all de-ephasis values, it was found that 0x130 is a right value. Where 0x13 is driver level and 0 is de-emphasis. Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patchStefan Roese2008-08-21-24/+13
| | | | | | | | | | | | | This patch fixes some minor issues introduced with the patch: ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika: - Rework memory-queue and PLB arbiter optimization code, that the local variable is not needed anymore. This removes one #ifdef. - Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead of XXX+ 0x01). This was not introduced by Prodyut, just a copy-paste problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,Prodyut Hazarika2008-08-21-5/+38
| | | | | | | | | | | | | | | PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* fdt: rework fdt_fixup_ethernet() to use env instead of bd_tKumar Gala2008-08-21-8/+8
| | | | | | | | | | Move to using the environment variables 'ethaddr', 'eth1addr', etc.. instead of bd->bi_enetaddr, bi_enet1addr, etc. This makes the code a bit more flexible to the number of ethernet interfaces. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Adding bootlimit/bootcount feature for MPC5XXX on TQM5200 BoardsAxel Beierlein2008-08-21-0/+20
| | | | | | Tested with TQM5200S on STK52XX.200 Board Signed-off-by: Axel Beierlein <belatronix@web.de>
* Merge branch 'next' of git://git.denx.de/u-boot-avr32Haavard Skinnemoen2008-08-20-1/+4
|\ | | | | | | | | | | Conflicts: MAINTAINERS
| * Merge branch 'favr-32' of git://git.denx.de/u-boot-avr32Haavard Skinnemoen2008-08-06-21/+29
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: MAINTAINERS MAKEALL Makefile
| * | Add support for the hammerhead (AVR32) boardJulien May2008-07-30-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May <mailinglist@miromico.ch> [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | | Clean up usage of icache_disable/dcache_disableKumar Gala2008-08-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in disabling the icache on 7xx/74xx/86xx parts and not also flushing the icache. All callers of invalidate_l1_instruction_cache() call icache_disable() right after. Make it so icache_disable() calls invalidate_l1_instruction_cache() for us. Also, dcache_disable() already calls dcache_flush() so there is no point in the explicit calls of dcache_flush(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ColdFire: Multiple fixes for M5282EVBTsiChung Liew2008-08-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Incorrect CFG_HZ value, change 1000000 to 1000. Rename #waring to #warning. RAMBAR1 uses twice in start.S, rename the later to FLASHBAR. Insert nop for DRAM setup. And, env_offset in linker file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | | ColdFire: Implement SBF feature for M5445EVBTsiChung Liew2008-08-14-23/+302
| | | | | | | | | | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | | ColdFire: Add SSPI feature for MCF5445xTsiChung Liew2008-08-14-6/+172
| | | | | | | | | | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2008-08-14-32/+32
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| * | | s3c24x0: Update NAND driver to new API.Scott Wood2008-08-13-32/+32
| | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
* | | | Merge branch 'Makefile' of git://git.denx.de/u-boot-armWolfgang Denk2008-08-13-3/+3
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| * | | | drivers/mtd/nand: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2008-08-13-3/+3
| |/ / / | | | | | | | | | | | | | | | | | | | | rename CFG_NAND_LEGACY to CONFIG_NAND_LEGACY Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | | | Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-08-13-194/+242
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| * | | Merge branch 'master' of git://www.denx.de/git/u-boot-at91Wolfgang Denk2008-08-12-1/+1
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| | * | | at91: move arch-at91sam9 to arch-at91Jean-Christophe PLAGNIOL-VILLARD2008-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | | | NAND boot: MPC8313ERDB supportScott Wood2008-08-12-107/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Note that with older board revisions, NAND boot may only work after a power-on reset, and not after a warm reset. I don't have a newer board to test on; if you have a board with a 33MHz crystal, please let me know if it works after a warm reset. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | NAND: Davinci driver updatesSergey Kubushyn2008-08-12-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Here comes a trivial patch to cpu/arm926ejs/davinci/nand.c. Unfortunately I don't have hardware handy so I can not test it at the moment but changes are rather trivial so it should work. It would be nice if somebody with a hardware checked it anyways. Signed-off-by: Sergey Kubushyn <ksi@koi8.net>
| * | | | NAND: Update 4xx NDFC driver to match updated nand subsystemStefan Roese2008-08-12-42/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the 4xx NAND driver ndfc.c to match the new infrastructure from the updated NAND subsystem. This NAND subsystem was recently synced again with the Linux 2.6.22 MTD/NAND subsystem. Tested successfully on AMCC Sequoia and Bamboo. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | Fixing coding style issuesWilliam Juul2008-08-12-16/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Fixing leading white spaces - Fixing indentation where 4 spaces are used instead of tab - Removing C++ comments (//), wherever I introduced them Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | Remove white space at end.William Juul2008-08-12-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | | Update MTD to that of Linux 2.6.22.1William Juul2008-08-12-54/+44
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot changed in the Linux MTD code, since it was last ported from Linux to U-Boot. This patch takes U-Boot NAND support to the level of Linux 2.6.22.1 and will enable support for very large NAND devices (4KB pages) and ease the compatibility between U-Boot and Linux filesystems. This patch is tested on two custom boards with PPC and ARM processors running YAFFS in U-Boot and Linux using gcc-4.1.2 cross compilers. MAKEALL ppc/arm has some issues: * DOC/OneNand/nand_spl is not building (I have not tried porting these parts, and since I do not have any HW and I am not familiar with this code/HW I think its best left to someone else.) Except for the issues mentioned above, I have ported all drivers necessary to run MAKEALL ppc/arm without errors and warnings. Many drivers were trivial to port, but some were not so trivial. The following drivers must be examined carefully and maybe rewritten to some degree: cpu/ppc4xx/ndfc.c cpu/arm926ejs/davinci/nand.c board/delta/nand.c board/zylonite/nand.c Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Stig Olsen <stig.olsen@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | | | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-08-12-141/+141
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| * | | MPC8272ADS: fix build error: 'bd_t' has no member named 'pci_clk'Wolfgang Denk2008-08-12-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2008-08-12-2/+2
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| | * \ \ Merge branch 'master' of git://www.denx.de/git/u-boot-armWolfgang Denk2008-08-12-2/+2
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| | | * | | i.MX31: Fix mx31_gpio_mux() function and MUX_-macros.Magnus Lilja2008-08-11-2/+2
| | | | |/ | | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Correct the mx31_gpio_mux() function to allow changing all i.MX31 IOMUX contacts instead of only the first 256 ones as is the case prior to this patch. Add missing MUX_* macros and update board files to use the new macros. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
| * | | | ads5121: fix compiler warnings (unused variables)Wolfgang Denk2008-08-12-3/+1
| |/ / / | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | 85xx: Rename CONFIG_NR_CPUS to CONFIG_NUM_CPUSKumar Gala2008-08-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Use CONFIG_NUM_CPUS to match existing define used by 86xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
| * | | POWERPC 86xx: Move BAT setup code to CBecky Bruce2008-08-11-119/+25
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This is needed because we will be possibly be locating devices at physical addresses above 32bits, and the asm preprocessing does not appear to deal with ULL constants properly. We now call write_bat in lib_ppc/bat_rw.c. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
| * | | mpc5121: Move iopin features from board specific to common files.Kenneth Johansson2008-08-05-1/+50
| | | | | | | | | | | | | | | | | | | | | | | | And in the process eliminate some duplicate register defines. Signed-off-by: Kenneth Johansson <kenneth@southpole.se>
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