summaryrefslogtreecommitdiff
path: root/cpu
Commit message (Collapse)AuthorAgeLines
* Add "chip_config" command for PPC4xx bootstrap configurationStefan Roese2009-07-24-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a generic command for programming I2C bootstrap eeproms on PPC4xx. An implementation for Canyonlands board is included. The command name is intentionally chosen not to be PPC4xx specific. This way other CPU's/SoC's can implement a similar command under the same name, perhaps with a different syntax. Usage on Canyonlands: => chip_config Available configurations (I2C address 0x52): 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100 800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100 800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100 1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 *** 1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88 => chip_config 600-nor Using configuration: 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 done (dump via 'i2c md 52 0.1 10') Reset the board for the changes to take effect Other 4xx boards will be migrated to use this command soon as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Dirk Eibach <eibach@gdsys.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* ppc4xx: Fix missing freqOPB for 405EPDirk Eibach2009-07-24-0/+2
| | | | | | | | In cpu/ppc4xx/speed.c initialization of sysInfo->freqOPB for 405EP was left out for no obvious reason. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix TLB reset problem with recent 44x imagesStefan Roese2009-07-24-2/+7
| | | | | | | | | | | | | | | | | Patch d873133f [ppc4xx: Add Sequoia RAM-booting target] broke "normal" booting on some 44x platforms. This breakage is only noticed in some cases while powercycling. As it seems, the code in question in start.S didn't invalidate TLB #0. This makes sense since this TLB is used for the bootrom mapping. With the patch mentioned above even TLB #0 got invalidated resulting in an error later on. This patch now fixes this issue by only invalidating TLB #0 in the RAM- booting case. Tested succesfully on Sequoia and Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <Eibach@gdsys.de>
* unify HOST_CFLAGS and HOSTCFLAGSMike Frysinger2009-07-23-1/+1
| | | | | | | | The top build system sets up HOSTCFLAGS a bit and exports it, but other places use HOST_CFLAGS instead. Unify the two as HOSTCFLAGS so that the values stay in sync. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* fec_mxc: driver for FEC ethernet controller on i.MX27Ilya Yanok2009-07-22-0/+10
| | | | | Signed-off-by: Ilya Yanok <yanok@emcraft.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* rm9200 ethernet driver: board-specific quirk (csb337)David Brownell2009-07-22-4/+18
| | | | | | | | | | | CSB337 boards originally shipped with MicroMonitor, not U-Boot; and with a version using a different convention for recording Ethernet addresses than anyone else. To avoid breaking Linux when it uses U-Boot, have it use the same convention on that hardware. Signed-off-by: David Brownell <dbrownell@users.sourceforge.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-23-14/+37
|\
| * ARM Cortex A8: Move OMAP3 specific reset handlerMinkyu Kang2009-07-22-14/+37
| | | | | | | | | | | | | | Because of the reset_cpu is soc specific, should be move to soc Cc: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | 85xx, 86xx: Add common board_add_ram_info()Peter Tyser2009-07-22-41/+98
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, 85xx and 86xx boards would display DRAM information on bootup such as: ... I2C: ready DRAM: Memory controller interleaving enabled: Bank interleaving! 2 GB FLASH: 256 MB ... This patch moves the printing of the DRAM controller configuration to a common board_add_ram_info() function which prints out DDR type, width, CAS latency, and ECC mode. It also makes the DDR interleaving information print out in a more sane manner: ... I2C: ready DRAM: 2 GB (DDR2, 64-bit, CL=4, ECC on) DDR Controller Interleaving Mode: bank FLASH: 256 MB ... Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fieldsPeter Tyser2009-07-22-2/+2
| | | | | | | | | | | | | | | | Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match the 86xx user's manual and other Freescale architectures Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Blackfin: split cpu COBJS into multilinesMike Frysinger2009-07-18-1/+7
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: add os log functionsMike Frysinger2009-07-18-1/+31
| | | | | | | | | | | | | | | | Part of the mini Blackfin ABI with operating systems is that they can use 0x4f0-0x4f8 to pass log buffers to/from bootloaders. So add support to U-Boot for reading the log buffer. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2009-07-19-224/+0
|\ \
| * | nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directoryStefan Roese2009-07-16-224/+0
| | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | | OMAP3 Fix compiler warning for v7_flush_dcache_allTom Rix2009-07-18-0/+3
| |/ |/| | | | | | | | | | | | | | | | | | | | | | | | | On build of omap3 targets in MAKEALL, the *.ERR files have cpu.c: In function 'cleanup_before_linux': cpu.c:64: warning: implicit declaration of function 'v7_flush_dcache_all' cpu.c:64: warning: implicit declaration of function 'get_device_type The functions v7_flush_dcache_all and get_device_type are declared in include/asm-arm/arch-omap3/sys_proto.h, so use this file to declare the functions. Signed-off-by: Tom Rix <Tom.Rix@windriver.com>
* | stdio/device: rework function naming conventionJean-Christophe PLAGNIOL-VILLARD2009-07-18-9/+9
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | So far the console API uses the following naming convention: ======Extract====== typedef struct device_t; int device_register (device_t * dev); int devices_init (void); int device_deregister(char *devname); struct list_head* device_get_list(void); device_t* device_get_by_name(char* name); device_t* device_clone(device_t *dev); ======= which is too generic and confusing. Instead of using device_XX and device_t we change this into stdio_XX and stdio_dev This will also allow to add later a generic device mechanism in order to have support for multiple devices and driver instances. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Edited commit message. Signed-off-by: Wolfgang Denk <wd@denx.de>
* usb: mpc834x: added support of the MPH USB controller in addition to the DR oneValeriy Glushkov2009-07-14-0/+2
| | | | | Signed-off-by: Valeriy Glushkov <gvv@lstec.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* MPC512x: factor out common codeWolfgang Denk2009-07-14-1/+122
| | | | | | | | | | | | | | Now that we have 3 boards for the MPC512x it turns out that they all use the very same fixed_sdram() code. This patch factors out this common code into cpu/mpc512x/fixed_sdram.c and adds a new header file, include/asm-ppc/mpc512x.h, with some macros, inline functions and prototype definitions specific to MPC512x systems. Signed-off-by: Wolfgang Denk <wd@denx.de> Cc: Stefan Roese <sr@denx.de> Cc: Reinhard Arlt <reinhard.arlt@esd-electronics.com>
* Merge branch 'master' of /home/wd/git/u-boot/masterWolfgang Denk2009-07-14-11/+509
|\
| * Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-13-2/+188
| |\
| | * at91: Introduction of at91sam9g10 SOC.Sedji Gaouaou2009-07-12-0/+1
| | | | | | | | | | | | | | | | | | | | | AT91sam9g10 is an ARM 926ej-s SOC. It is an evolution of the at91sam9261 with a faster clock speed: 266/133MHz. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| | * at91: Introduction of at91sam9g45 SOC.Sedji Gaouaou2009-07-12-2/+187
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | AT91sam9g45 series is an ARM 926ej-s SOC family clocked at 400/133MHz. It embeds USB high speed host and device, LCD, DDR2 RAM, and a full set of peripherals. The first board that embeds at91sam9g45 chip is the AT91SAM9G45-EKES. On the board you can find 2 USART, USB high speed, a 480*272 LG lcd, ethernet, gpio/joystick/buttons. Signed-off-by: Sedji Gaouaou <sedji.gaouaou@atmel.com>
| * | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2009-07-13-0/+296
| |\ \
| | * | sh: unify linker scriptJean-Christophe PLAGNIOL-VILLARD2009-07-08-0/+296
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | all sh boards use the same cpu linker script so move it to cpu/$(CPU) that could be overwrite in following order SOC BOARD via the corresponding config.mk tested on r2dplus Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Cc: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
| * | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-07-13-7/+23
| |\ \
| | * | ppc4xx: Set default PCI device ID for 405EP boardsMatthias Fuchs2009-07-10-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Current code only sets the PCI vendor id to 0x1014 and leaved device id to 0x0000. Ths patch .... a) uses the correct PCI_VENDOR_ID_IBM macro for this b) sets the default device ID as stated in the UM to 0x0156 by using PCI_DEVICE_ID_IBM_405GP for this. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()Matthias Fuchs2009-07-10-5/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch moves some basic PCI initialisation from the 4xx cpu_init_f() to cpu/ppc4xx/4xx_pci.c. The original cpu_init_f() function enabled the 405EP's internal arbiter in all situations. Also the HCE bit in cpc0_pci is always set. The first is not really wanted for PCI adapter designs and the latter is a general bug for PCI adapter U-Boots. Because it enables PCI configuration by the system CPU even when the PCI configuration has not been setup by the 405EP. The one and only correct place is in pci_405gp_init() (see "Set HCE bit" comment). So for compatibility reasons the arbiter is still enabled in any case, but from weak pci_pre_init() so that it can be replaced by board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | mpc83xx: USB: fix: access of ehci struct elementsVivek Mahajan2009-07-09-2/+2
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | It fixes the access to the 'ehci' struct elements for mpc83xx which should have been taken care of in 4ef01010aa4799c759d75e67007fdd3a38c88c8a Sorry about that. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Remy Bohmer <linux@bohmer.net>
* | | board support patch for phyCORE-MPC5200B-tinyJon Smirl2009-07-10-0/+3
|/ / | | | | | | | | | | | | | | | | | | Add support for the Phytec phyCORE-MPC5200B-tiny. Code originally from Pengutronix.de. Created CONFIG_SYS_ATA_CS_ON_TIMER01 define for when IDE CS is on Timer 0/1 Signed-off-by: Jon Smirl <jonsmirl@gmail.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
* | ppc4xx: Make pll_write globalMatthias Fuchs2009-07-08-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes pll_write on PPC405EP boards global and callable from C code. pll_write can be used to dynamically modify the PLB:PCI divider as it is required for 33/66 MHz pci adapters based on the 405EP. board_early_init_f() is a good place to do that (check M66EN signal and call pll_write() when it is required). Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Remove compilation warning "pci_async_enabled defined but not used"Stefan Roese2009-07-08-0/+2
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Implement is_pci_host() for 405 CPUsMatthias Fuchs2009-07-08-3/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements the is_pci_host() function in a similiar way as it is used on 440 targets. The former path with CONFIG_PCI_HOST == PCI_HOST_AUTO does not build on 405EP targets because checking the PCI arbiter is different. So putting the fixed code into a separate function makes the code more readable. Also using is_pci_host() on 405 brings 405 and 440 PCI code a little bit closer. In preparation for an upcoming 405EP based PMC module I made this function weak so that it can be overwritten from board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fixed PPC4xx debug compilation error in uic.cAlessio Centazzo2009-07-08-1/+1
| | | | | | | | | | | | | | | | | | | | This patch fixes a debug compilation error for PPC4xx platforms, all other architectures are not affected by this change. The 'handler' pointer was undefined. The fix is exercised and has effect only if DEBUG is defined. Signed-off-by: Alessio Centazzo acpatin@yahoo.com Signed-off-by: Stefan Roese <sr@denx.de>
* | 4xx: Fix compilation warnings and MQ registers dump in SPD DDR2 codeFelix Radensky2009-07-08-17/+25
|/ | | | | | | | | | This patch fixes printf format string compilation warnings in several debug statements. It also fixes the dump of DDR controller MQ registers found on some 44x and 46x platforms. The current register dump code uses incorrect DCRs to access these registers. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanup; update CHANGELOGWolfgang Denk2009-07-07-5/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-07-07-277/+1818
|\ | | | | | | | | | | | | Conflicts: drivers/spi/Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * arm: Kirkwood: arch specific updated for ehci-Kirkwood driver supportPrafulla Wadaskar2009-07-06-5/+1
| | | | | | | | | | | | This patch abstracts Kirkwood arch specific changes to support ehci-kirkwood driver Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * arm nomadik: use 1000 as HZ value and rewrite timer codeAlessandro Rubini2009-07-06-139/+27
| | | | | | | | | | | | | | | | | | | | | | | | This sets CONFIG_SYS_HZ to 1000 as required, and completely rewrites timer code, which is now both correct and much smaller. Unused functions like udelay_masked() have been removed as no driver uses them, even the ones that are not currently active for this board. mtu.h is copied literally from the kernel sources. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm nomadik: cleanup resetAlessandro Rubini2009-07-06-12/+1
| | | | | | | | | | | | | | | | There is only one public release of the Nomadik chip, so the ifdef in reset code as well as a define in the config file are not needed Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
| * at91: Add CAN init functionDaniel Gorsulowski2009-07-06-0/+30
| | | | | | | | | | | | | | | | | | To enable CAN init, CONFIG_CAN has to be defined in the board config file and at91_can_hw_init() has to be called in the board specific code. CAN is available on AT91SAM9263 and AT91CAP9 SoC. Signed-off-by: Daniel Gorsulowski <Daniel.Gorsulowski@esd.eu>
| * S3C24x0: extract interrupts from timerJean-Christophe PLAGNIOL-VILLARD2009-07-06-21/+56
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm920t/interrupts: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2009-07-06-6/+6
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * move L2 cache enable/disable function to cache.c in the omap3 SoC directoryKim, Heung Jun2009-07-06-68/+104
| | | | | | | | | | | | Signed-off-by: HeungJun, Kim <riverful.kim@samsung.com> CC: Dirk Behme <dirk.behme@googlemail.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * arm: Kirkwood: Basic SOCs supportPrafulla Wadaskar2009-07-06-0/+670
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Kirkwood family controllers are highly integrated SOCs based on Feroceon-88FR131/Sheeva-88SV131/arm926ejs cpu core. SOC versions supported:- 1) 88F6281-A0 define CONFIG_KW88F6281_A0 2) 88F6192-A0 define CONFIG_KW88F6192_A0 Other supported features:- 1) get_random_hex() fucntion 2) PCI Express port initialization 3) NS16550 driver support Contributors: Yotam Admon <yotam@marvell.com> Michael Blostein <michaelbl@marvell.com Reviewed-by: Ronen Shitrit <rshitrit@marvell.com> Acked-by: Stefan Rose <sr@denx.de> Signed-off-by: Prafulla Wadaskar <prafulla@marvell.com>
| * s3c64xx: move the reset_cpu functionMinkyu Kang2009-06-26-16/+36
| | | | | | | | | | | | | | | | Because of the reset_cpu is soc specific, should be move to soc And read reset value from SYS_ID register instead of hard code this patch also supports s3c6410 Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * mx27: basic cpu supportIlya Yanok2009-06-21-0/+533
| | | | | | | | | | | | This patch adds generic code to support Freescale's i.MX27 SoCs. Signed-off-by: Ilya Yanok <yanok@emcraft.com>
| * i.MX31: Create a common device file.Magnus Lilja2009-06-21-0/+57
| | | | | | | | Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
| * MX31: Add NAND SPL for i.MX31.Magnus Lilja2009-06-21-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds the NAND SPL framework needed to boot i.MX31 boards from NAND. It has been tested on a i.MX31 PDK board with large page NAND. Small page NANDs should work as well, but this has not been tested. Note: The i.MX31 NFC uses a non-standard layout for large page NANDs, whether this is compatible with a particular setup depends on how the NAND device is programmed by the flash programmer (e.g. JTAG debugger). The patch is based on the work by Maxim Artamonov. Signed-off-by: Maxim Artamonov <scn1874@yandex.ru> Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
| * ARM1136: Introduce CONFIG_PRELOADER macro.Magnus Lilja2009-06-21-12/+12
| | | | | | | | | | | | | | | | | | Currently CONFIG_ONENAND_IPL is used in a number of #ifdef's in start.S. In preparation for adding support for NAND SPL the macro CONFIG_PRELOADER is introducted and replaces the CONFIG_ONENAND_IPL in start.S. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
| * at91: unify nor boot supportJean-Christophe PLAGNIOL-VILLARD2009-06-21-2/+284
| | | | | | | | | | | | the lowlevel init sequence is the same so unify it Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
generated by cgit v1.1 at 2024-12-21 08:18:37 +0000