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* Merge branch 'master' of git://www.denx.de/git/u-boot-avr32Wolfgang Denk2008-07-07-22/+90
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| * avr32: Fix SPI portmux initializationHaavard Skinnemoen2008-06-20-22/+34
| | | | | | | | | | | | | | Use the new GPIO manipulation functions to set up the chip select lines, and make sure both busses use GPIO for chip select control. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
| * avr32: Add GPIO manipulation functionsPeter Ma2008-06-20-0/+56
| | | | | | | | | | | | | | | | Adds GPIO manipulation functions for AVR32 AP7 platform. Signed-off-by: Peter Ma <pma@mediamatech.com> [haavard.skinnemoen@atmel.com: coding style fixup, slight simplification] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc83xxWolfgang Denk2008-07-07-1/+5
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| * | fix system config overwrite @ MPC834x and MPC8313Andre Schwarz2008-06-25-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During 83xx setup the "System I/O configuration register high" gets overwritten with user defined value if CFG_SICRH is defined. Regarding to the MPC834x manual (Table 5-28 reve.1) bits 28+29 of SICRH must keep their reset value regardless of configuration. On my board (using RGMII) those bits are set after reset - yet it's unclear where they come from. The patch keeps both bits on MPC834x and MPC8313. Signed-off-by: Andre Schwarz <andre.schwarz@matrix-vision.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | mpc83xx: move CPU_TYPE_ENTRY over to processor.hKim Phillips2008-06-25-1/+0
| |/ | | | | | | | | | | | | | | | | | | to avoid this: cpu.c:47:1: warning: "CPU_TYPE_ENTRY" redefined In file included from cpu.c:33: /home/kim/git/u-boot/include/asm/processor.h:982:1: warning: this is the location of the previous definition Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | ppc4xx: Rename CONFIG_XILINX_ML300 to CONFIG_XILINX_405Michal Simek2008-07-06-1/+1
| | | | | | | | | | | | | | | | This change helps with better handling with others Xilinx based platform. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of ssh+git://mercury.denx.de/home/wd/git/u-boot/masterWolfgang Denk2008-07-06-22/+47
|\ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/amirix/ap1000/serial.c board/exbitgen/exbitgen.c board/exbitgen/flash.c board/ml2/serial.c board/xilinx/ml300/serial.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Cleanup out-or-tree building for some boards (.depend)Wolfgang Denk2008-07-02-2/+2
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Cleanup: fix out-of-tree building for some boardsWolfgang Denk2008-07-02-14/+30
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | Cleanup: replace hard-wired $(AR) 'crv' settings by $(ARFLAGS)Wolfgang Denk2008-07-02-2/+2
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | mpc8260: add fdt_fixup_ethernet supportEsben Haabendal2008-07-01-0/+5
| | | | | | | | | | | | | | | | | | | | | Add support for updating mac-address and local-mac-address in fdt for all MPC8260 targets. Signed-off-by: Esben Haabendal <eha@doredevelopment.dk>
| * | i.MX31: fixed CTRL-C detectionJuergen Kilb2008-07-01-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Register URXD contains status information in bits [15..8]. With status bit 15 set, CTRL-C was reported as 0x8003 instead of 0x03. Therefore CTRL-C was not detected. To solve this, bits [15..8] were masked out now. Signed-off-by: Juergen Kilb <J.Kilb@gmx.de> Acked-by: Felix Radensky <felix@embedded-sol.com>
| * | Coding Style CleanupWolfgang Denk2008-06-28-1/+1
| | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | MMC: Consolidate MMC/SD command definitionsHaavard Skinnemoen2008-06-28-6/+9
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This moves the MMC and SD Card command definitions from include/asm/arch/mmc.h into include/mmc.h. These definitions are given by the MMC and SD Card standards, not by any particular architecture. There's a lot more room for consolidation in the MMC drivers which I'm hoping to get done eventually, but this patch is a start. Compile-tested for all avr32 boards as well as lpc2292sodimm and lubbock. This should cover all three mmc drivers in the tree. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | ppc4xx: Fix 460EX errata with CPU lockup upon high AHB trafficStefan Roese2008-06-30-2/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch implements a fix provided by AMCC so that the lockup upon simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur anymore: Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA. This errata is not officially available yet. I'll update the comment to add the errata number later. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix problem in gpio_config()Stefan Roese2008-06-23-2/+2
|/ | | | | | | As pointed out by Guennadi Liakhovetski (thanks), pin2 is already shifted left by one. So the additional shift is bogus. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix 4xx build issueAnatolij Gustschin2008-06-19-1/+1
| | | | | | | | | | | | | | Building for 4xx doesn't work since commit 4dbdb768: In file included from 4xx_pcie.c:28: include/asm/processor.h:971: error: expected ')' before 'ver' make[1]: *** [4xx_pcie.o] Error 1 This patch fixes the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-5/+5
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mipsWolfgang Denk2008-06-11-28/+17
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| * [MIPS] cpu/mips/Makefile: Split [CS]OBJS onto separate linesShinya Kuribayashi2008-06-07-18/+10
| | | | | | | | | | | | Also get rid of some #ifdefs in *.c files. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Rename Alchemy processor configs into CONFIG_SOC_*Shinya Kuribayashi2008-06-07-9/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | CONFIG_SOC_AU1X00 Common Alchemy Au1x00 stuff. All Alchemy processor based machines need to have this config as a system type specifier. CONFIG_SOC_AU1000, CONFIG_SOC_AU1100, CONFIG_SOC_AU1200, CONFIG_SOC_AU1500, CONFIG_SOC_AU1550 Machine type specifiers. Each port should have one of aboves. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Update <asm/addrspace.h> headerShinya Kuribayashi2008-06-05-3/+3
| | | | | | | | | | | | | | - Fix traditional KSEG names - Replace PHYSADDR with CPHYSADDR Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
| * [MIPS] Kill unused <version.h> inclusionsShinya Kuribayashi2008-06-05-3/+0
| | | | | | | | Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-fdtWolfgang Denk2008-06-11-22/+13
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| * | Remove the deprecated CONFIG_OF_FLAT_TREEGerald Van Baren2008-06-09-4/+0
| | | | | | | | | | | | | | | | | | | | | Use CONFIG_OF_LIBFDT instead to support flattened device trees. It is cleaner, has better functionality, and is better supported. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
| * | Convert mpc7448hpc2 to CONFIG_OF_LIBFDTGerald Van Baren2008-06-09-20/+15
| |/ | | | | | | | | | | | | | | | | | | | | | | | | This was configured to use the deprecated CONFIG_OF_FLAT_TREE, change to CONFIG_OF_LIBFDT. WARNING: This conversion is untested because I do not have a board to test it on. NOTE: The FDT blob (DTS) must have an /aliases/ethernet0 and (optionally) /aliases/ethernet1 property for the ethernet to work. Signed-off-by: Gerald Van Baren <vanbaren@cideas.com>
* | Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-06-11-547/+656
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| * | ppc4xx: Fix misspelled CONFIG_440SPE/440EPX/GRX config optionsStefan Roese2008-06-06-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | We use upper case letters for the AMCC processor defines (like CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and not CONFIG_440SPe. This patch fixes the last misspelled config options. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Remove superfluous dram_init() call or replace it by initdram()Stefan Roese2008-06-03-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Historically the 405 U-Boot port had a dram_init() call in early init stage. This function was still called from start.S and most of the time coded in assembler. This is not needed anymore (since a long time) and boards should implement the common initdram() function in C instead. This patch now removed the dram_init() call from start.S and removes the empty implementations that are scattered through most of the 405 board ports. Some older board ports really implement this dram_init() though. These are: csb272 csb472 ERIC EXBITGEN W7OLMC W7OLMG I changed those boards to call this assembler dram_init() function now from their board specific initdram() instead. This *should* work, but please test again on those platforms. And it is perhaps a good idea that those boards use some common 405 SDRAM initialization code from cpu/ppc4xx at some time. So further patches welcome here. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Use new 4xx SDRAM controller enable defines in common ECC codeStefan Roese2008-06-03-2/+3
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix common ECC generation code for 440GP style platformsStefan Roese2008-06-03-7/+34
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes the common 4xx ECC code really usable on 440GP style platforms. Since the IBM DDR controller used on 440GP/GX/EP/GR is not register compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT we need to make some processor dependant defines used later on by the driver. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Change Kilauea to use the common DDR2 init functionStefan Roese2008-06-03-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch changes the kilauea and kilauea_nand (for NAND booting) board port to not use a board specific DDR2 init routine anymore. Now the common code from cpu/ppc4xx is used. Thanks to Grant Erickson for all his basic work on this 405EX early bootup. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Consolidate PPC4xx SDRAM/DDR/DDR2 defines, part1Stefan Roese2008-06-03-151/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch removes all SDRAM related defines from the PPC4xx headers ppc405.h and ppc440.h. This is needed since now some 405 PPC's use the same SDRAM controller as 440 systems do (like 405EX and 440SP). It also introduces new defines for the equipped SDRAM controller based on which PPC variant is used. There new defines are: used on 405GR/CR/EP and some Xilinx Virtex boards. used on 440GP/GX/EP/GR. used on 440EPx/GRx. used on 405EX/r/440SP/SPe/460EX/GT. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.SStefan Roese2008-06-03-126/+80
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch consolidates the 405 and 440 parts of the NAND booting code selected via CONFIG_NAND_SPL. Now common code is used to initialize the SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc. Only *after* running from this location, nand_boot() is called. Please note that the initsdram() call is now moved from nand_boot.c to start.S. I experienced problems with some boards like Kilauea (405EX), which don't have internal SRAM (OCM) and relocation needs to be done to SDRAM before the NAND controller can get accessed. When initdram() is called later on in nand_boot(), this can lead to problems with variables in the bss sections like nand_ecc_pos[]. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
| * | ppc4xx: Enable Primordial Stack for 40x and Unify ECC HandlingGrant Erickson2008-06-03-259/+526
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | PPC4xx: Simplified post_word_{load, store}Grant Erickson2008-06-03-15/+11
| | | | | | | | | | | | | | | | | | | | | This patch simplifies post_word_{load,store} by using the preprocessor to eliminate redundant, copy-and-pasted code. Signed-off-by: Grant Erickson <gerickson@nuovations.com>
* | | Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2008-06-11-73/+265
|\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: include/asm-ppc/fsl_lbc.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | 85xx/86xx: Move to dynamic mgmt of LAWsKumar Gala2008-06-11-7/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
| * | | FSL LAW: Keep track of LAW allocationsKumar Gala2008-06-11-17/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | Added the upmconfig() function for 85xx.Sergei Poselenov2008-06-11-0/+66
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | MPC85xx: Beautify boot output of L2 cache configurationWolfgang Grandegger2008-06-10-9/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The boot output is now aligned poperly with other boot output lines, e.g.: FLASH: 128 MB L2: 512 KB enabled Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
| * | | 85xx: Add setting of cache props in the device tree.Kumar Gala2008-06-10-0/+128
| | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | 85xx: expose cpu identificationKumar Gala2008-06-10-36/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current cpu identification code is used just to return the name of the processor at boot. There are some other locations that the name is useful (device tree setup). Expose the functionality to other bits of code. Also, drop the 'E' suffix and add it on by looking at the SVR version when we print this out. This is mainly to allow the most flexible use of the name. The device tree code tends to not care about the 'E' suffix. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define itKumar Gala2008-06-09-2/+6
| | | | | | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | MPC85xx: Change traps.c to not reference non-addressable memoryBecky Bruce2008-06-09-3/+5
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* | | MPC86xx: Change traps.c to not reference non-addressable memoryBecky Bruce2008-06-06-1/+7
|/ / | | | | | | | | | | | | | | | | | | | | | | Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd to prevent us from trying to access non-mapped memory. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* | PPC4xx: Simplified post_word_{load, store}Grant Erickson2008-06-03-15/+11
| | | | | | | | | | | | | | This patch simplifies post_word_{load,store} by using the preprocessor to eliminate redundant, copy-and-pasted code. Signed-off-by: Grant Erickson <gerickson@nuovations.com>
* | atmel_spi: Driver for the Atmel SPI controllerHans-Christian Egtvedt2008-06-03-0/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This adds a driver for the SPI controller found on most AT91 and AVR32 chips, implementing the new SPI API. Changed in v4: - Update to new API - Handle zero-length transfers appropriately. The user may send a zero-length SPI transfer with SPI_XFER_END set in order to deactivate the chip select after a series of transfers with chip select active. This is useful e.g. when polling the status register of DataFlash. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* | SPI API improvementsHaavard Skinnemoen2008-06-03-21/+58
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch gets rid of the spi_chipsel table and adds a handful of new functions that makes the SPI layer cleaner and more flexible. Instead of the spi_chipsel table, each board that wants to use SPI gets to implement three hooks: * spi_cs_activate(): Activates the chipselect for a given slave * spi_cs_deactivate(): Deactivates the chipselect for a given slave * spi_cs_is_valid(): Determines if the given bus/chipselect combination can be activated. Not all drivers may need those extra functions however. If that's the case, the board code may just leave them out (assuming they know what the driver needs) or rely on the linker to strip them out (assuming --gc-sections is being used.) To set up communication parameters for a given slave, the driver needs to call spi_setup_slave(). This returns a pointer to an opaque spi_slave struct which must be passed as a parameter to subsequent SPI calls. This struct can be freed by calling spi_free_slave(), but most driver probably don't want to do this. Before starting one or more SPI transfers, the driver must call spi_claim_bus() to gain exclusive access to the SPI bus and initialize the hardware. When all transfers are done, the driver must call spi_release_bus() to make the bus available to others, and possibly shut down the SPI controller hardware. spi_xfer() behaves mostly the same as before, but it now takes a spi_slave parameter instead of a spi_chipsel function pointer. It also got a new parameter, flags, which is used to specify chip select behaviour. This may be extended with other flags in the future. This patch has been build-tested on all powerpc and arm boards involved. I have not tested NIOS since I don't have a toolchain for it installed, so I expect some breakage there even though I've tried fixing up everything I could find by visual inspection. I have run-time tested this on AVR32 ATNGW100 using the atmel_spi and DataFlash drivers posted as a follow-up. I'd like some help testing other boards that use the existing SPI API. But most of all, I'd like some comments on the new API. Is this stuff usable for everyone? If not, why? Changed in v4: - Build fixes for various boards, drivers and commands - Provide common struct spi_slave definition that can be extended by drivers - Pass a struct spi_slave * to spi_cs_activate and spi_cs_deactivate - Make default bus and mode build-time configurable - Override default SPI bus ID and mode on mx32ads and imx31_litekit. Changed in v3: - Add opaque struct spi_slave for controller-specific data associated with a slave. - Add spi_claim_bus() and spi_release_bus() - Add spi_free_slave() - spi_setup() is now called spi_setup_slave() and returns a struct spi_slave - soft_spi now supports four SPI modes (CPOL|CPHA) - Add bus parameter to spi_setup_slave() - Convert the new i.MX32 SPI driver - Convert the new MC13783 RTC driver Changed in v2: - Convert the mpc8xxx_spi driver and the mpc8349emds board to the new API. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com> Tested-by: Guennadi Liakhovetski <lg@denx.de>
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