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* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-287/+349
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| * ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval boardStefan Roese2007-06-01-92/+129
| | | | | | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
| * NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.cStefan Roese2007-06-01-20/+54
| | | | | | | | | | | | | | | | | | | | This patch adds hardware ECC support to the NDFC driver. It also changes the register access from using the "simple" in32/out32 functions to the in_be32/out_be32 functions, which make sure that the access is correctly synced. This is the only recommended access to SoC registers in the current Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: 44x DDR driver code cleanup and small fix for BambooStefan Roese2007-06-01-175/+166
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-06-01-1/+6
| | | | | | | | | | | | | | Add config option for 180 degree advance clock control as needed for the AMCC Luan eval board. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/tur/git/u-boot#motionproWolfgang Denk2007-05-28-8/+4
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| * | MPC5XXX, Motion-PRO: Fix PHY initialization problem.Bartlomiej Sieka2007-05-27-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After being reset in mpc5xxx_fec_init_phy(), PHY goes into FX mode, in which networking does not function. This commit switches PHY to TX mode by clearing the FX_SEL bit of Mode Control Register. It also reverses commit 008861a2f3ef2c062744d733787c7e530a1b8761, i.e., a temporary workaround. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
| * | MPC5xxx: Change names of defines related to IPB and PCI clocks.Bartlomiej Sieka2007-05-27-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Both CFG_PCISPEED_66 and CFG_IPBSPEED_133 are misnamed, as defining them does not cause PCI or IPB clocks to run at the specified speed. Instead, they configure divisors used to calculate said clocks. This patch renames the defines according to their real function. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Bartlomiej Sieka <tur@semihalf.com>
* | | ppc4xx: Add 405 support to 4xx NAND driver ndfc.cStefan Roese2007-05-22-4/+4
| | | | | | | | | | | | | | | | | | | | | This patch adds support for 405 PPC's to the 4xx NAND driver ndfc.c. This is in preparation for the new AMCC 405EZ. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Fix problem in 405EZ OCM initializationStefan Roese2007-05-21-1/+1
| | | | | | | | | | | | | | | | | | | | | As spotted by Bruce Adler this patch fixes an initialization problem for the 405EZ OCM. Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-05-16-43/+279
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| * | | Fix memory initialization on MPC8349E-mITXTimur Tabi2007-05-01-5/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Define CFG_DDR_SDRAM_CLK_CNTL for the MPC8349E-mITX and MPC8349E-mITX-GP. This allows ddr->sdram_clk_cntl to be properly initialized. This is necessary on some ITX boards, notably those with a revision 3.1 CPU. Also change spd_sdram() in cpu/mpc83xx/spd_sdram.c to not write anything into ddr->sdram_clk_cntl if CFG_DDR_SDRAM_CLK_CNTL is not defined. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Michael Benedict <MBenedict@twacs.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc83xx: replace elaborate boottime verbosity with 'clocks' commandKim Phillips2007-05-01-5/+13
| | | | | | | | | | | | | | | | | | | | | | | | and fix CPU: to align with Board: display text. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc83xx: minor fixups for 8313rdb introductionKim Phillips2007-04-25-0/+1
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| * | | mpc83xx: Add generic PCI setup code.Scott Wood2007-04-23-1/+192
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Board code can now request the generic setup code rather than having to copy-and-paste it for themselves. Boards should be converted to use this once they're tested with it. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | mpc83xx: Add 831x support to speed.c.Scott Wood2007-04-23-26/+42
| | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | mpc83xx: Change PVR_83xx to PVR_E300C1-3, and update checkcpu().Scott Wood2007-04-23-4/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than misleadingly define PVR_83xx as the specific type of 83xx being built for, the PVR of each core revision is defined. checkcpu() now prints the core that it detects, rather than aborting if it doesn't find what it thinks it wants. Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | mpc83xx: Recognize SPR values for MPC8311 and MPC8313.Scott Wood2007-04-23-0/+12
| | | | | | | | | | | | | | | | Signed-off-by: Scott Wood <scottwood@freescale.com>
| * | | Merge git://www.denx.de/git/u-bootKim Phillips2007-04-23-2621/+10523
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| * | | | Fix two bugs for MPC83xx DDR2 controller SPD InitXie Xiaobo2007-04-12-3/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There are a few bugs in the cpu/mpc83xx/spd_sdram.c the first bug is that the picos_to_clk routine introduces a huge rounding error in 83xx. the second bug is that the mode register write recovery field is tWR-1, not tWR >> 1.
* | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-microblazeWolfgang Denk2007-05-16-236/+88
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| * | | | | add: reading special purpose registersMichal Simek2007-05-08-2/+2
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| * | | | | add: Microblaze V5 exception handlingMichal Simek2007-05-08-2/+8
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| * | | | | Merge git://www.denx.de/git/u-bootMichal Simek2007-05-08-2917/+10472
| |\ \ \ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: include/asm-microblaze/microblaze_intc.h include/linux/stat.h
| * | | | | | new: USE_MSR_INTR supportMichal Simek2007-05-07-6/+21
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| * | | | | | fix: interrupt handlerMichal Simek2007-05-07-10/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | remove asm code
| * | | | | | fix: remove asm codeMichal Simek2007-05-07-223/+17
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| * | | | | | fix: clean interruptMichal Simek2007-05-07-3/+13
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| * | | | | | fix: interrupt handler for multiple sourcesMichal Simek2007-05-07-10/+13
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| * | | | | | 16bit read/write little endianMichal Simek2007-04-21-0/+33
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* | | | | | | Merge with /home/tur/git/u-boot#motionproWolfgang Denk2007-05-15-0/+11
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| * | | | | [MPC5xxx] There are networking problems on the Motion-PRO board withBartlomiej Sieka2007-05-07-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | current PHY initalization code (tftp timeouts all the time). This commit temporarily disables PHY initalization sequence to make the networking operational, until a fix is found.
* | | | | | 5xxx: write MAC address to mac-address and local-mac-addressTimur Tabi2007-05-05-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-by: Grant Likely <grant.likely@secretlab.ca>
* | | | | | [PATCH] Use PVR to distinguish MPC5200B from MPC5200 in boot messageGrzegorz Wianecki2007-05-05-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC5200B systems are incorrectly reported as MPC5200 in U-Boot start-up message. Use PVR to distinguish between the two variants, and print proper CPU information. Signed-off-by: Grzegorz Wianecki <grzegorz.wianecki@gmail.com> Signed-off-by: Bartlomiej Sieka <tur@semihalf.com> Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
* | | | | | Coding stylke cleanup; update CHANGELOG.Wolfgang Denk2007-05-05-11/+11
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-05-05-9/+21
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| * \ \ \ \ \ Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-04-29-1113/+1396
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| * | | | | ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.Matthias Fuchs2007-04-24-9/+21
| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc85xxWolfgang Denk2007-05-05-75/+95
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| * | | | | | Cleaned up some 85xx PCI bugsAndy Fleming2007-05-02-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | | | Add support for the 8568 MDS boardAndy Fleming2007-05-02-2/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | | | Reworked 85xx speed detection codeAndy Fleming2007-04-23-36/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed the code to read the registers and calculate the clock rates, rather than using a "switch" statement. Idea from Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | | | Support 1G size on 8548Andy Fleming2007-04-23-2/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | e500v2 and newer cores support 1G page sizes. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | | | Only set ddrioovcr for 8548 rev1.Andy Fleming2007-04-23-6/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | | | Tweak DDR ECC error counterAndy Fleming2007-04-23-2/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * | | | | | 85xx: write MAC address to mac-address and local-mac-addressTimur Tabi2007-04-23-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | | | | Some 85xx cpu cleanupsAndy Fleming2007-04-23-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Cleaned up the TSR[WIS] clearing * Cleaned up DMA initialization Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * | | | | | Add cpu support for the 8544Andy Fleming2007-04-23-2/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Recognize new SVR values, and add a few register definitions Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * | | | | | u-boot: Fix e500 v2 core reset bugZang Roy-r619112007-04-23-6/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The following patch fixes the e500 v2 core reset bug. For e500 v2 core, a new reset control register is added to reset the processor. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
| * | | | | | u-boot: v2: Remove the fixed TLB and LAW entrynubmerZang Roy-r619112007-04-23-12/+4
| | |/ / / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW entry number to control the loop. This can reduce the potential risk for the 85xx processor increasing its TLB adn LAW entry number. Signed-off-by: Swarthout Edward <swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
generated by cgit v1.1 at 2024-09-19 19:06:40 +0000