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| * mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLYBecky Bruce2008-11-10-10/+10
| | | | | | | | | | | | | | | | | | | | | | We define CONFIG_MONITOR_BASE_EARLY to define the initial location of the bootpage in flash. Use this to create an early mapping definition for the FLASH, and change the early_bats code to use this. This change facilitates the relocation of the flash since the early mappings are no longer tied to the final location of the flash. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc86xx: Use SRR0/1/rfi to enable address translation, not blrBecky Bruce2008-11-10-11/+8
| | | | | | | | | | | | | | | | | | | | Using a mtmsr/blr means that you have to be executing at the same virtual address once you enable translation. This is unnecessarily restrictive, and is not really how this is usually done. Change it to use the more common mtspr SRR0/SRR1 and rfi method. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * mpc86xx: Move setup_bats into cpu_init_fBecky Bruce2008-11-10-5/+4
| | | | | | | | | | | | | | | | | | | | | | In order to later allow for a physical relocation of the flash, setup_bats, which sets up the final BAT mapping for the board, needs to happen *after* init_laws(). Otherwise, there will be no window programmed for the flash at the new physical location at the point when we change the mmu translation. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * Merge commit 'wd/master'Jon Loeliger2008-11-10-286/+1166
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| * | powerpc: change 86xx SMP boot methodBecky Bruce2008-11-04-73/+277
| | | | | | | | | | | | | | | | | | | | | | | | | | | We put the bootpg for the secondary cpus into memory and use BPTR to get to it. This is a step towards converting to the ePAPR boot methodology. Also, the code is written to deal properly with more than 4GB of RAM. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * | powerpc 86xx: Handle CCSR relocation earlierBecky Bruce2008-11-03-5/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently, the CCSR gets relocated while translation is enabled, meaning we need 2 BAT translations to get to both the old location and the new location. Also, the DEFAULT CCSR location has a dependency on the BAT that maps the FLASH region. Moving the relocation removes this unnecessary dependency. This makes it easier and more intutive to modify the board's memory map. Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same BAT for CCSR space. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* | | Moved initialization of PPC4xx EMAC to cpu_eth_init()Ben Warren2008-11-09-0/+14
| | | | | | | | | | | | | | | | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* | | Moved PPC4xx EMAC driver to drivers/netBen Warren2008-11-09-2128/+0
| | | | | | | | | | | | | | | | | | | | | Also changed path in all linker scripts that reference this driver Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* | | Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMACBen Warren2008-11-09-9/+1
| | | | | | | | | | | | | | | | | | | | | All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* | | Moved initialization of MPC8XX SCC to cpu_eth_init()Ben Warren2008-11-09-0/+4
| | | | | | | | | | | | | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Moved initialization of MPC8220 FEC to cpu_eth_init()Ben Warren2008-11-09-0/+13
| | | | | | | | | | | | | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Moved initialization of QE Ethernet controller to cpu_eth_init()Ben Warren2008-11-09-1/+37
| | | | | | | | | | | | | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Moved initialization of FCC Ethernet controller to cpu_eth_initBen Warren2008-11-09-1/+30
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Affected boards: Several MPC8xx boards Several MPC8260/MPC8272 boards Several MPC85xx boards Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Fix typo in cpu/mpc85xx/cpu.cBen Warren2008-11-09-1/+1
| | | | | | | | | | | | | | | | | | CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | net: Move initialization of Au1x00 SoC ethernet MAC to cpu_eth_initShinya Kuribayashi2008-11-09-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | This patch will move au1x00_eth_initialize from net/eth.c to cpu_eth_init as a part of ongoing eth_initialize cleanup work. The function ret value is also fixed as it should be negative on fail. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | | Moved initialization of IXP4XX_NPE Ethernet controller to cpu_eth_init()Ben Warren2008-11-09-0/+9
| |/ |/| | | | | | | | | Also, removed the driver initialization from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2008-11-09-15/+47
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| * | Change to use "do_div" macroTomohiro Masubuchi2008-11-04-13/+45
| | | | | | | | | | | | Signed-off-by: Tomohiro Masubuchi <tomohiro_masubuchi@tripeaks.co.jp>
| * | ARM926EJ-S: relocate OMAP specific 'cpuinfo.c' into OMAP directoryRoman Mashak2008-11-04-2/+2
| |/ | | | | | | | | | | | | OMAP identification is implemented in 'cpuinfo.c' and located in ARM926EJ-S directory. It makes sense to place this file in OMAP specific subdirectory, i.e. cpu/arm926ejs/omap Signed-off-by: Roman Mashak <romez777@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2008-11-09-269/+1119
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| * | ColdFire: Fix compilation errorTsiChung Liew2008-11-03-9/+9
| | | | | | | | | | | | | | | | | | | | | The error was caused by the change for strmhz() in cpu.c. A few of them were one extra close parenthesis. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | ColdFire: Add MCF5301x CPU and M53017EVB supportTsiChung Liew2008-11-03-49/+304
| | | | | | | | | | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | ColdFire: Add SBF support for M52277EVBTsiChung Liew2008-11-03-17/+541
| | | | | | | | | | | | | | | | | | Add serial boot support Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | ColdFire: Relocate FEC's GPIO and mii functions protocolsTsiChung Liew2008-11-03-3/+185
| | | | | | | | | | | | | | | | | | | | | Place FEC pin assignments in cpu_init.c from platform's mii.c Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
| * | ColdFire: Modules header files cleanupTsiChung Liew2008-11-03-191/+80
| |/ | | | | | | | | | | | | | | | | | | | | | | Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* | Consolidate MAX/MIN definitionsAndy Fleming2008-11-02-2/+0
|/ | | | | | | There were several, now there is one (two if you count the lower-case versions). Signed-off-by: Andy Fleming <afleming@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2008-11-01-305/+128
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| * Blackfin: fix up UART status bit handlingMike Frysinger2008-10-23-12/+60
| | | | | | | | | | | | | | | | Some Blackfin UARTs are read-to-clear while others are write-to-clear. This can cause problems when we poll the LSR and then later try and handle any errors detected. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: small cpu init optimization while setting interrupt maskMike Frysinger2008-10-23-5/+2
| | | | | | | | | | | | | | Use the sti instruction to set the initial interrupt mask rather than banging on the core IMASK MMR to save both space and time. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: set initial stack correctly according to Blackfin ABIMike Frysinger2008-10-23-3/+3
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: make baud calculation more accurateMike Frysinger2008-10-23-4/+4
| | | | | | | | | | | | | | | | We should use the algorithm in the Linux kernel so that the UART divisor calculation is more accurate. It also fixes problems on some picky UARTs that have sampling anomalies. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: decode hwerrcause/excause when crashingMike Frysinger2008-10-23-2/+40
| | | | | | | | | | | | Having to decode hwerrcause/excause values is a pain, so automate it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: fix register dump messagesMike Frysinger2008-10-23-1/+5
| | | | | | | | | | | | Make sure we report RETI/IPEND correctly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: don't bother displaying reboot msg when crashingMike Frysinger2008-10-23-5/+1
| | | | | | | | | | | | | | The hang function already tells you to reboot, so no point in showing it twice. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: enable support for nested interruptsMike Frysinger2008-10-23-4/+10
| | | | | | | | | | | | | | During cpu init, make sure we initialize the CEC properly so that interrupts can fire and be handled while U-Boot is running. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: drop unused cache flush codeMike Frysinger2008-10-23-231/+1
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: unify cache handling codeMike Frysinger2008-10-23-35/+0
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: only enable hardware error irq by defaultMike Frysinger2008-10-23-3/+2
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | 74xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheDave Liu2008-10-31-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch is following the commit 392438406041415fe64ab8748ec5ab5ad01d1cf7 mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com> also, the r2 is used as global data pointer. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2008-10-30-1/+1
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| * | mpc83xx pci: Round up memory size in inbound window.Scott Wood2008-10-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The current calculation will fail to cover all memory if its size is not a power of two. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc86xxWolfgang Denk2008-10-30-16/+4
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| * | | 86xx: remove the redundant r2 global data pointer saveDave Liu2008-10-30-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 67256678f00c09b0a7f19e862e5c1847553d31bc add the another global data pointer save, but in fact the global data pointer will be initialized in the board_init_r, so remove it such as the 85xx/83xx family. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
| * | | 86xx: remove the unused code for 86xx familyDave Liu2008-10-30-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I believe these code was copied from 74xx family, but for 86xx, it is unused. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
| * | | 86xx: Move the clear_tlbs before MMU turn onDave Liu2008-10-30-1/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | We must invalidate TLBs before MMU turn on, but currently the code is not, if there are some stale TLB entry valid in the TLBs, it will cause strange issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* | | Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-29-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | i386: Renamed show_boot_progress in assembler codeGraeme Russ2008-10-28-10/+10
| | | | | | | | | | | | | | Renamed show_boot_progress in assembler init phase to show_boot_progress_asm to avoid link conflicts with C version Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-27-5/+22
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| * | 85xx: Fix the incorrect register used for DDR erratum1Dave Liu2008-10-24-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | 85xx: Add basic e500mc core supportKumar Gala2008-10-24-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-07-16 21:35:46 +0000