summaryrefslogtreecommitdiff
path: root/cpu
Commit message (Collapse)AuthorAgeLines
* 83xx: Add eSDHC support on 8379 EMDS boardAndy Fleming2009-02-16-0/+14
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add eSDHC support for 8536 DSAndy Fleming2009-02-16-0/+15
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* Eliminated arch-specific mmc header requirementAndy Fleming2009-02-16-0/+191
| | | | | | | | | | The current MMC infrastructure relies on the existence of an arch-specific header file. This isn't necessary, and a couple drivers were forced to implement dummy files to meet this requirement. Instead, we move the stuff in those header files into a more appropriate place, and eliminate the stubs and the #include of asm/arch/mmc.h Signed-off-by: Andy Fleming <afleming@freescale.com>
* Convert mmc_init to mmc_legacy_initAndy Fleming2009-02-16-3/+3
| | | | | | This is to get it out of the way of incoming MMC framework Signed-off-by: Andy Fleming <afleming@freescale.com>
* Eliminate support for using MMC as memoryAndy Fleming2009-02-16-40/+0
| | | | | | MMC cards are not memory, so we stop treating them that way. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 32bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b108122009-02-16-1/+8
| | | | | | | This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
* 86xx: Update CPU info output on bootupPeter Tyser2009-02-16-41/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 86xx: Reset updatePeter Tyser2009-02-16-61/+19
| | | | | | | | | | Update the 86xx reset sequence to try executing a board-specific reset function. If the board-specific reset is not implemented or does not succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard reset procedure than the previous method and allows all board peripherals to be reset if needed. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* fsl-ddr: Allow system to boot if we have more than 4G of memoryKumar Gala2009-02-16-1/+1
| | | | | | | | | | Previously if we >=4G of memory and !CONFIG_PHYS_64BIT we'd report an error and hang. Instead of doing that since DDR is mapped in the lowest priority LAWs we setup the DDR controller and the max amount of memory we report back is what we can map (CONFIG_MAX_MEM_MAPPED) Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Becky Bruce <beckyb@kernel.crashing.org>
* mpc85xx: Add support for the P2020Srikanth Srinivasan2009-02-16-0/+3
| | | | | | | | | | | Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-47/+27
| | | | | | | | | Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala2009-02-16-0/+4
| | | | | | | | If we only have one controller we can completely ignore how memctl_intlv_ctl is set. Otherwise other levels of code get confused and think we have twice as much memory. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Format cpu freq printing to handle 8 coresKumar Gala2009-02-16-3/+5
| | | | | | | Only print 4 cpu freq per line. This way when we have 8 cores its a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Fix initialization of the SDRAM_CODT registerCarolyn Smith2009-02-12-5/+2
| | | | | | | | | This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2 initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits. Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Autocalibration can set RDCC to over aggressive value.Adam Graham2009-02-12-29/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanup; update CHANGELOGWolfgang Denk2009-02-12-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 8xx serial, smc: Coding-Style cleanup serial SMC driverHeiko Schocher2009-02-11-48/+24
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* 8xx serial, smc: add configurable SMC Rx buffer lenHeiko Schocher2009-02-11-37/+57
| | | | | | | | | | | | | | This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN. With this option it is possible to allow the receive buffer for the SMC on 8xx to be greater then 1. In case CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the old version. When defining CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE must be defined to setup the maximum idle timeout for the SMC. Signed-off-by: Heiko Schocher <hs@denx.de>
* Fix MPC8260 with ethernet on SCCksi@koi8.net2009-02-09-1/+1
| | | | | | | | This fixes MPC8260 compilation with ethernet on SCC. Probably was a typo or something... Signed-off-by: Sergey Kubushyn <ksi@koi8.net> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* 82xx serial, smc: Coding-Style cleanup serial SMC driverHeiko Schocher2009-02-10-36/+18
| | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* 82xx serial, smc: add configurable SMC Rx buffer lenHeiko Schocher2009-02-10-37/+60
| | | | | | | | | | | | | | This patch adds the configuration option CONFIG_SYS_SMC_RXBUFLEN. With this option it is possible to allow the receive buffer for the SMC on 82xx to be greater then 1. In case CONFIG_SYS_SMC_RXBUFLEN == 1 this driver works as the old version. When defining CONFIG_SYS_SMC_RXBUFLEN also CONFIG_SYS_MAXIDLE must be defined to setup the maximum idle timeout for the SMC. Signed-off-by: Heiko Schocher <hs@denx.de>
* ppc: Move CONFIG_MAX_MEM_MAPPED to common config.hKumar Gala2009-02-10-3/+0
| | | | | | | | Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent between the two current users (lib_ppc/board.c, 44x SPD DDR2). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* mpc86xx: Add support to populate addr map based on BATsBecky Bruce2009-02-10-0/+27
| | | | | | | If CONFIG_ADDR_MAP is enabled, update the address map whenever we write a bat. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarityKumar Gala2009-02-07-13/+13
| | | | | | | | | | The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-coldfireWolfgang Denk2009-02-07-3/+10
|\
| * Coldfire: M5271: Allow board header file to specify clock multiplierRichard Retanubun2009-02-06-1/+6
| | | | | | | | | | | | | | | | | | M5271 dynamic clock multiplier. It is currently fixed at 100MHz. Allow the board header file to set their own multiplier and divider. Added the #define for the multiplier and divider to the cpu header file. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
| * Coldfire: M5271EVB: Remove usage of CONFIG_SYS_FECI2CRichard Retanubun2009-02-06-1/+2
| | | | | | | | | | | | | | Discontinue the use of CONFIG_SYS_FECI2C (only used by M5271EVB). Use read-modify-write to activate the FEC pins without disabling I2C. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
| * Coldfire: Fix half-baud UART by adding M5271 to Coldfire v2 core listRichard Retanubun2009-02-06-1/+2
| | | | | | | | | | | | | | | | | | Added the CONFIG_M5271 to the list of Coldfire V2 processor. This was causing the bus clock (not CPU clock) to be declared twice as fast as it actually is. This causes UARTS to operate at half the specified baudrate. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2009-02-07-121/+108
|\ \
| * | Blackfin: dynamically update UART speed when initializingMike Frysinger2009-02-05-91/+43
| | | | | | | | | | | | | | | | | | | | | | | | | | | Previously, booting over the UART required the baud rate to be known ahead of time. Using a bit of tricky simple math, we can calculate the new board rate based on the old divisors. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Robin Getz <rgetz@blackfin.uclinux.org>
| * | Blackfin: add support for fast SPI reads with Boot ROMMike Frysinger2009-02-05-8/+17
| | | | | | | | | | | | | | | | | | | | | Newer Blackfin boot roms support using the fast SPI read command rather than just the slow one. If the functionality is available, then use it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: check for reserved settings in DDR MMRsMike Frysinger2009-02-05-0/+7
| | | | | | | | | | | | | | | | | | | | | Some bits of the DDR MMRs should not be set. If they do, bad things may happen (like random failures or hardware destruction). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: set default voltage levels for BF538/BF539 partsMike Frysinger2009-02-05-0/+3
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * | Blackfin: use on-chip syscontrol() rom function when availableMike Frysinger2009-02-05-22/+38
| |/ | | | | | | | | | | | | | | Newer Blackfin's have an on-chip rom with a syscontrol() function that needs to be used to properly program the memory and voltage settings as it will include (possibly critical) factory tested bias values. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2009-02-07-5/+26
|\ \
| * | ppc4xx: Make PCIE support selectableDirk Eibach2009-02-06-3/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | On some platforms PCIE support is not required, but would be included because the cpu supports it. To reduce fooprint it is now configurable via CONFIG_PCI_DISABLE_PCIE. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Only fixup opb attached UARTsMatthias Fuchs2009-02-06-2/+22
| |/ | | | | | | | | | | | | | | | | This patch updates the fdt UART clock fixup code to only touch CPU internal UARTs on 4xx systems. Only these UARTs are definitely clocked by gd->uart_clk. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2009-02-07-0/+397
|\ \ | |/ |/|
| * ADS5121 Add IC Ident Module (IIM) supportMartha Marx2009-02-03-0/+397
| | | | | | | | | | | | | | | | | | | | | | | | IIM (IC Identification Module) is the fusebox for the mpc5121. Use #define CONFIG_IIM to turn on the clock for this module use #define CONFIG_CMD_FUSE to add fusebox commands. Fusebox commands include the ability to read the status, read the register cache, override the register cache, program the fuses and sense them. Signed-off-by: Martha Marx <mmarx@silicontkx.com> Signed-off-by: John Rigby <jrigby@freescale.com>
* | Blackfin: rewrite cache handling functionsMike Frysinger2009-02-02-46/+72
| | | | | | | | | | | | | | Take the cache flush functions from the kernel as they use hardware loops in order to get optimal performance. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: enable --gc-sectionsMike Frysinger2009-02-02-0/+1
| | | | | | | | | | | | | | Start building all Blackfin boards with -ffunction-sections/-fdata-sections and linking with --gc-sections. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Blackfin: dont check baud if it wont actually get usedMike Frysinger2009-02-02-1/+5
|/ | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-02-01-0/+3169
|\
| * Initial support for Nomadik 8815 development boardAlessandro Rubini2009-01-24-0/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | The NMDK8815 board is distributed by ST Microelectornics. Other (proprietary) code must be run to unlock the CPU before U-Boot runs. doc/README.nmdk8815 outlines the boot sequence. This is the initial port, with basic infrastructure and a working serial port. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * OMAP3: Add common board, interrupt and system infoDirk Behme2009-01-24-0/+895
| | | | | | | | | | | | Add common board, interrupt and system info code. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
| * OMAP3: Add common clock, memory and low level codeDirk Behme2009-01-24-0/+1098
| | | | | | | | | | | | Add common clock, memory and low level code Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
| * OMAP3: Add common cpu and start codeDirk Behme2009-01-24-0/+922
| | | | | | | | | | | | Add common cpu and start code. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2009-02-01-12/+57
|\ \
| * | mgcoge make ether_scc.c work with CONFIG_NET_MULTIGary Jennejohn2009-01-24-12/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is needed for mgcoge because it uses two ethernet drivers. Add a check for the presence of the PIGGY board on mgcoge. Without this board networking cannot work and the initialization must be aborted. Only allocate rtx once to prevent DPRAM exhaustion. Initialize ether_scc.c and the keymile-specific HDLC driver (to be added soon) in eth.c. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | sh: sh_eth: Change new network APINobuhiro Iwamatsu2009-01-24-0/+8
| |/ | | | | | | | | | | | | sh_eth used old network API. This patch changed new API. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
generated by cgit v1.1 at 2024-11-05 10:30:47 +0000