Commit message (Collapse) | Author | Age | Lines | |
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* | Change arbitration to round-robin for SMP linux. | Jon Loeliger | 2006-05-19 | -6/+9 |
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* | Enable dual DDR controllers and interleaving. | Jon Loeliger | 2006-05-19 | -121/+494 |
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* | Remove L2 Cache invalidate polling. | Jon Loeliger | 2006-05-19 | -11/+17 |
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* | Remove unneeded INIT_RAM_LOCK cache twiddling. | Haiying Wang | 2006-05-10 | -2/+3 |
| | | | | | | Correctly tracks r29 as global data pointer now. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> | |||
* | Cleanup whitespaces and style issues. | Jon Loeliger | 2006-04-27 | -411/+339 |
| | | | | | | | Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft. | |||
* | Initial support for MPC8641 HPCN board. | Jon Loeliger | 2006-04-26 | -0/+4699 |
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* | MPC5200: enable snooping of DMA transactions on XLB even if no PCI | Wolfgang Denk | 2006-04-18 | -4/+4 |
| | | | | | is configured; othrwise DMA accesses aren't cache coherent which causes for example USB to fail. | |||
* | Some code cleanup | Wolfgang Denk | 2006-04-16 | -111/+111 |
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* | Fix Lite500B support: Merge with /home/raj/git/u-boot.l5200b_pci | Wolfgang Denk | 2006-04-06 | -5/+5 |
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| * | Set SDelay register in the DDR controller for the MPC5200B chip. | Rafal Jaworowski | 2006-03-29 | -5/+5 |
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* | | Merge with /home/sr/git/u-boot/4xx-sdram | Wolfgang Denk | 2006-04-05 | -34/+342 |
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| * | | Updates to common PPC4xx onboard (DDR)SDRAM init code (405 and 440) | Stefan Roese | 2006-03-31 | -34/+342 |
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 405 SDRAM: - The SDRAM parameters can now be defined in the board config file and the 405 SDRAM controller values will be calculated upon bootup (see PPChameleonEVB). When those settings are not defined in the board config file, the register setup will be as it is now, so this implementation should not break any current design using this code. Thanks to Andrea Marson from DAVE for this patch. 440 DDR: - Added function sdram_tr1_set to auto calculate the TR1 value for the DDR. - Added ECC support (see p3p440). Patch by Stefan Roese, 17 Mar 2006 | |||
* | | Fix CONFIG_SKIP_LOWLEVEL_INIT dependency in cpu/arm920t/start.S | Wolfgang Denk | 2006-04-03 | -1/+2 |
| | | | | | | | | Patch by Peter Menzebach, 13 Oct 2005 [DNX#2006040142000473] | |||
* | | GCC-4.x fixes: clean up global data pointer initialization for all boards. | Wolfgang Denk | 2006-03-31 | -233/+195 |
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* | | Merge with http://www.denx.de/git/u-boot.git | Markus Klotzbuecher | 2006-03-24 | -453/+4384 |
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| * | Add support for MPC859/866 Rev. A.0 | Wolfgang Denk | 2006-03-18 | -3/+8 |
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| * | Support for DDR with 32-data path. Addotional notes on injecting | Rafal Jaworowski | 2006-03-16 | -12/+49 |
| | | | | | | | | multiple-bit errors. | |||
| * | Add support for ECC DDR initialization on MPC83xx. | Marian Balakowicz | 2006-03-14 | -22/+108 |
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| * | Add DMA support for MPC83xx. | Marian Balakowicz | 2006-03-14 | -0/+85 |
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| * | Add sync in do_reset() routine for MPC83xx after RPR register | Marian Balakowicz | 2006-03-14 | -0/+2 |
| | | | | | | | | | | was written to. It is need on some targets when BAT translation is enabled. | |||
| * | Add Dcbz(), Dcbi() and Dcbf() routines for MPC83xx. | Marian Balakowicz | 2006-03-14 | -0/+34 |
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| * | Correct shift offsets in icache_status and dcache_status for MPC83xx. | Marian Balakowicz | 2006-03-14 | -2/+2 |
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| * | Apply SoC concept to arm926ejs CPUs, i.e. move the SoC specific timer and | Wolfgang Denk | 2006-03-13 | -167/+531 |
| | | | | | | | | | | cpu_reset code from cpu/$(CPU) into the new cpu/$(CPU)/$(SOC) directories Patch by Andreas Engel, 13 Mar 2006 | |||
| * | Fix problem with updated PCI code in cpu/ppc4xx/405gp_pci.c | Stefan Roese | 2006-03-13 | -1/+1 |
| | | | | | | | | Patch by Stefan Roese, 13 Mar 2006 | |||
| * | cpu/ppc4xx/start.S : exceptions are enabled after relocation | Stefan Roese | 2006-03-13 | -23/+18 |
| | | | | | | | | Patch by Cedric Vincent, 6 June 2005 | |||
| * | au1x00_eth.c: check malloc return value and abort if it failed | Wolfgang Denk | 2006-03-13 | -2/+6 |
| | | | | | | | | Patch by Andrew Dyer, 26 Jul 2005 | |||
| * | Fix bug in [id]cache_status commands for MPC85xx processors; | Wolfgang Denk | 2006-03-13 | -2/+2 |
| | | | | | | | | | | | | should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005 | |||
| * | Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#mpc83xx | Wolfgang Denk | 2006-03-12 | -209/+349 |
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| | * | Enable address translation on MPC83xx | Kumar Gala | 2006-02-10 | -179/+298 |
| | | | | | | | | | | | | Patch by Kumar Gala, 10 Feb 2006 | |||
| | * | Decopuled setting of OR/BR and LBLAWBAR/LBLAWAR on MPC83xx | Kumar Gala | 2006-01-25 | -28/+21 |
| | | | | | | | | | | | | Patch by Kumar Gala, 25 Jan 2006 | |||
| | * | Only disable the MPC83xx watchdog if its enabled out of reset. | Kumar Gala | 2006-01-11 | -0/+6 |
| | | | | | | | | | | | | | | | If its disabled out of reset SW can later enable it if so desired Patch by Kumar Gala, 11 Jan 2006 | |||
| | * | Allow config of GPIO direction & data registers at boot on 83xx | Kumar Gala | 2006-01-11 | -0/+8 |
| | | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006 | |||
| | * | Enable time handling on 83xx | Kumar Gala | 2006-01-11 | -0/+10 |
| | | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006 | |||
| | * | Make System IO Config Registers board configurable on MPC83xx | Kumar Gala | 2006-01-11 | -2/+6 |
| | | | | | | | | | | | | Patch by Kumar Gala, 11 Jan 2006 | |||
| * | | Merge with git://git.kernel.org/pub/scm/boot/u-boot/u-boot.git#ft_infr | Wolfgang Denk | 2006-03-12 | -0/+38 |
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| | * | | Add helper function for generic flat device tree fixups for mpc83xx | Kumar Gala | 2006-01-11 | -0/+38 |
| | |/ | | | | | | | | | | Patch by Kumar Gala 11 Jan 2006 | |||
| * | | Fix PCIDF calculation in cpu/mpc8260/speed.c for MPC8280EC | Wolfgang Denk | 2006-03-12 | -8/+19 |
| | | | | | | | | | | | | Patch by KokHow Teh, 16 Jun 2005 | |||
| * | | Coding Style cleanup | Wolfgang Denk | 2006-03-12 | -171/+165 |
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| * | | Add missing Blackfin files. | Wolfgang Denk | 2006-03-12 | -0/+3135 |
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| * | | More GCC 4.x woes | Wolfgang Denk | 2006-03-11 | -1/+2 |
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| * | | Some code cleanup for GCC 4.x | Wolfgang Denk | 2006-03-11 | -2/+2 |
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* | | | Added config options CFG_MONAHANS_RUN_MODE_OSC_RATIO and | Markus Klotzbuecher | 2006-03-24 | -2/+15 |
| | | | | | | | | | | | | | | | CFG_MONAHANS_TURBO_RUN_MODE_RATIO for configuring the Monahans core frequency. | |||
* | | | delta board: DA9030 initialization and i2c support. Some minor changes to | Markus Klotzbuecher | 2006-03-24 | -5/+14 |
|/ / | | | | | | | make the pxa i2c driver work with the monahans cpu. | |||
* | | Cleanup (get rid of debug code that sneaked in) | Wolfgang Denk | 2006-03-07 | -1/+0 |
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* | | Merge with /home/wd/git/u-boot/master | Wolfgang Denk | 2006-03-06 | -48/+42 |
|\ \ | | | | | | | | | | Code cleanup. | |||
| * | | Initial port to MCC200 board (work in progress) | Wolfgang Denk | 2006-02-22 | -1/+2 |
| | | | | | | | | | | | | Minimally modified patch by Bluetechnix, Vienna | |||
* | | | Cleanup of NAND support of delta board using the Monahans Data Flash | Markus Klotzbücher | 2006-03-06 | -1/+9 |
| | | | | | | | | | | | | Controller. | |||
* | | | Lots of new stuff: | Markus Klotzbücher | 2006-03-04 | -1/+1 |
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | * Debug message can be turned on and off. * Waiting for events now times out. * Implemented RESET command. * Added appropriate nand_bbt_descriptor and nand_oobinfo. Remaining Problems: * Read Status still behaves weird an returns invalid stuff sometimes. * ECC Placement does not respect our scheme in nand_oobinfo. | |||
* | | | All subsystem clocks not immediately need are turned at reset. | Markus Klotzbücher | 2006-02-28 | -0/+10 |
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* | | | Added GPIO initialization of DF signal. Still not working. | Markus Klotzbücher | 2006-02-28 | -0/+1 |
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