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* ppc4xx: Fix small merge problem in 4xx_enet.cStefan Roese2007-10-31-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add PPC405EX supportStefan Roese2007-10-31-100/+532
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming)Stefan Roese2007-10-31-0/+11
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial fdt support to 4xx (first needed on 405EX)Stefan Roese2007-10-31-0/+171
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Change PCIe status output to match common styleStefan Roese2007-10-31-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Disable debug output as defaultStefan Roese2007-10-31-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support addedStefan Roese2007-10-31-39/+54
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & KatmaiStefan Roese2007-10-31-1/+24
| | | | | | | | | | | | | | | | | 128MB seems to be the smallest possible value for the memory size for on PCIe port. With this change now the BAR's of the PCIe cards are accessible under U-Boot. One big note: This only works for PCIe port 0 & 1. For port 2 this currently doesn't work, since the base address is now 0xc0000000 (0xb0000000 + 2 * 0x08000000), and this is already occupied by CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean to change the base addresses completely and this change would have too much impact right now. This patch adds debug output to the 4xx pcie driver too. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idxStefan Roese2007-10-31-6/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platformsStefan Roese2007-10-31-4/+4
| | | | | | | | These files were introduced with the IBM 405GP but are currently used on all 4xx PPC platforms. So the name doesn't match the content anymore. This patch renames the files to 4xx_pci.c/h. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add a comment for 405EX PCIe endpoint configurationStefan Roese2007-10-31-0/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)Stefan Roese2007-10-31-419/+223
| | | | | | | | | | | | | | | (3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access the SDR registers of the PCIe ports. This makes the overall design clearer, since it removed a lot of switch statements which are not needed anymore. Also, the functions ppc4xx_init_pcie_rootport() and ppc4xx_init_pcie_entport() are merged into a single function ppc4xx_init_pcie_port(), since most of the code was duplicated. This makes maintainance and porting to other 4xx platforms easier. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)Stefan Roese2007-10-31-10/+10
| | | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)Stefan Roese2007-10-31-178/+3
| | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese <sr@denx.de>
* delta: Fix OHCI_REGS_BASE undeclared and wait_ms implicit declarationJean-Christophe PLAGNIOL-VILLARD2007-10-24-0/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* fix warning: no return statement in function returning non-voidJean-Christophe PLAGNIOL-VILLARD2007-10-24-7/+7
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* fix pxa255_idp boardMarcel Ziswiler2007-10-23-39/+42
| | | | | | | | | | | | | | | | | | | | | | | The pxa255_idp being an old unmaintained board showed several issues: 1. CONFIG_INIT_CRITICAL was still defined. 2. Neither CONFIG_MAC_PARTITION nor CONFIG_DOS_PARTITION was defined. 3. Symbol flash_addr was undeclared. 4. The boards lowlevel_init function was still called memsetup. 5. The TEXT_BASE was still 0xa3000000 rather than 0xa3080000. 6. Using -march=armv5 instead of -march=armv5te resulted in lots of 'target CPU does not support interworking' warnings on recent compilers. 7. The PXA's serial driver redefined FFUART, BTUART and STUART used as indexes rather than the register definitions from the pxa-regs header file. Renamed them to FFUART_INDEX, BTUART_INDEX and STUART_INDEX to avoid any ambiguities. 8. There were several redefinition warnings concerning ICMR, OSMR3, OSCR, OWER, OIER, RCSR and CCCR in the PXA's assembly start file. 9. The board configuration file was rather outdated. 10. The part header file defined the vendor, product and revision arrays as unsigned chars instead of just chars in the block_dev_desc_t structure. Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* 86xx: Allow for fewer DDR slots per memory controller.Jon Loeliger2007-10-16-9/+21
| | | | | | | | | | | | | As a direct correlation exists between DDR DIMM slots and SPD EEPROM addresses used to configure them, use the individually defined SPD_EEPROM_ADDRESS* values to determine if a DDR DIMM slot should have its SPD configuration read or not. Effectively, this now allows for 1 or 2 DIMM slots per memory controller. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* PXA USB OHCI: "usb stop" implementation.Rodolfo Giometti2007-10-15-0/+16
| | | | | | | | Some USB keys need to be switched off before loading the kernel otherwise they can remain in an undefined status which prevents them to be correctly recognized by the kernel. Signed-off-by: Rodolfo Giometti <giometti@linux.it>
* Fix warning differ in signedness in cpu/pxa/mmc.cJean-Christophe PLAGNIOL-VILLARD2007-10-13-3/+3
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch 'merge' of git://www.denx.de/git/u-boot-microblazeWolfgang Denk2007-10-13-5/+10
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| * [PATCH] Add support for design without interrupt controllerMichal Simek2007-09-24-0/+7
| | | | | | | | Polling timer
| * [FIX] resolve problem with cpu without barrel shifterMichal Simek2007-09-24-4/+2
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| * [FIX] repair email addressMichal Simek2007-09-24-1/+1
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| * synchronizition with mainlineMichal Simek2007-09-24-10/+5
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| * Merge ../u-bootMichal Simek2007-09-24-20/+24
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| * \ Merge git://www.denx.de/git/u-bootMichal Simek2007-09-11-1480/+3922
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| * \ \ Merge git://www.denx.de/git/u-boot into mergeMichal Simek2007-08-15-2665/+4804
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| * \ \ \ Merge git://www.denx.de/git/u-bootMichal Simek2007-08-07-533/+1100
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| * \ \ \ \ Merge git://www.denx.de/git/u-bootMichal Simek2007-08-05-0/+3119
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| * | | | | | [PATCH] Support time without timerMichal Simek2007-07-14-0/+7
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| * | | | | | [PATCH] Remove problem with disabled BARREL SHIFTERMichal Simek2007-07-13-4/+2
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| * | | | | | Merge git://www.denx.de/git/u-bootMichal Simek2007-07-13-385/+614
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| * | | | | | | [fix] email reparationMichal Simek2007-06-17-1/+1
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| * | | | | | | [FIX] fix microblaze file permitissionMichal Simek2007-06-17-0/+0
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* | | | | | | | Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-10-04-11/+17
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| * \ \ \ \ \ \ \ Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-10-02-0/+2
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| | * | | | | | | | Fix missing DECLARE_GLOBAL_DATA_PTR on CONFIG_LPC2292 in serialJean-Christophe PLAGNIOL-VILLARD2007-09-28-0/+2
| | | |_|_|_|_|_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | | | | | | | ppc4xx: Coding style cleanupStefan Roese2007-10-02-12/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | | | | | Program EPLD to force full duplex mode for PHY.Grzegorz Bernacki2007-10-02-4/+8
| |/ / / / / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
* | | | | | | | Move coloured led API to status_led.hPeter Pearse2007-09-18-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Improve indentation in drivers/at45.c
* | | | | | | | Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-09-18-14/+15
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| * | | | | | | Fix cases where DECLARE_GLOBAL_DATA_PTR was not declared as globalWolfgang Denk2007-09-15-14/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | | | | Final tidyPeter Pearse2007-09-11-0/+0
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* | | | | | | | Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-09-11-6/+10
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| * | | | | | | [MPC512x] Streamline frame handling in the FEC driverGrzegorz Bernacki2007-09-10-6/+9
| | |_|_|_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - convert frame size settings to be derived from a single base - set frame size to the recommended default value Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
| * | | | | | Remove compiler warning: target CPU does not support interworkingKyungmin Park2007-09-10-0/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
* | | | | | | Merge with git://www.denx.de/git/u-boot.gitPeter Pearse2007-09-10-85/+152
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| * | | | | | Merge with /home/raj/git/u-boot#440SPe_PCIe_fixesWolfgang Denk2007-09-08-71/+130
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| | * | | | | | [PPC440SPe] Improve PCIe configuration space accessGrzegorz Bernacki2007-09-07-31/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - correct configuration space mapping - correct bus numbering - better access to config space Prior to this patch, the 440SPe host/PCIe bridge was able to configure only the first device on the first bus. We now allow to configure up to 16 buses; also, scanning for devices behind the PCIe-PCIe bridge is supported, so peripheral devices farther in hierarchy can be identified. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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