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* NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.cStefan Roese2007-06-01-20/+54
| | | | | | | | | | This patch adds hardware ECC support to the NDFC driver. It also changes the register access from using the "simple" in32/out32 functions to the in_be32/out_be32 functions, which make sure that the access is correctly synced. This is the only recommended access to SoC registers in the current Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 44x DDR driver code cleanup and small fix for BambooStefan Roese2007-06-01-175/+166
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.Matthias Fuchs2007-04-24-9/+21
| | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-04-18-0/+4
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| * [Fix] Set the LED status register on the UC101 for the LXT971 PHY.Heiko Schocher2007-04-14-0/+4
| | | | | | | | | | | | clear the Display after reset. Signed-off-by: Heiko Schocher <hs@denx.de>
* | ppc4xx: Add output for bootrom location to 405EZ portsStefan Roese2007-04-18-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Now 405EZ ports also show upon bootup from which boot device they are configured to boot: U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) Bootstrap Option E - Boot ROM Location EBC (32 bits) 16 kB I-Cache 16 kB D-Cache Board: Acadia - AMCC PPC405EZ Evaluation Board Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix i2c divisor calcularion for PPC4xxJeffrey Mann2007-04-12-3/+1
|/ | | | | | | | | | | This patch fixes changes the i2c_init(...) function to use the function get_OPB_freq() rather than calculating the OPB speed by sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is specific per processor. The prior method was not and so was calculating the wrong speed for some PPC4xx processors. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-04-04-220/+353
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| * Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-03-31-1444/+7674
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| * | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-03-31-19/+49
| | | | | | | | | | | | | | | | | | | | | Additional RAM information is now printed upon powerup, like DDR2 frequency and CAS latency. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-03-31-48/+81
| | | | | | | | | | | | | | | | | | | | | | | | Fix a bug in the auto calibration routine. This driver now runs more reliable with the tested modules. It's also tested with 167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai. Signed-off-by: Stefan Roese <sr@denx.de>
| * | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-156/+226
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| | * | [PATCH] Add 4xx GPIO functionsStefan Roese2007-03-24-114/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | [PATCH] Clean up 40EZ/Acadia supportStefan Roese2007-03-24-42/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up all the open issue of the preliminary Acadia support. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Minor coding style cleanup.Wolfgang Denk2007-04-04-1/+1
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* | | | Merge with /home/wd/git/u-boot/custodian/u-boot-microblazeWolfgang Denk2007-04-04-8/+838
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| * | | | Support for XUPV2P boardMichal Simek2007-03-26-4/+33
| | | | | | | | | | | | | | | | | | | | | | | | | Reset support BSP autoconfig support
| * | | | [Microblaze][PATCH] part 2Michal Simek2007-03-11-8/+239
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | timer support interrupt controller support flash support ethernet support cache support board information support env support booting image support adding support for Xilinx ML401
| * | | | [Microblaze][PATCH]Michal Simek2007-03-11-0/+570
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | timer support interrupt controller support flash support ethernet support cache support board information support env support booting image support adding support for Xilinx ML401
* | | | | Fix some minor whitespace violations.Gerald Van Baren2007-03-31-2/+2
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* | | | | Add a flattened device tree (fdt) command (2 of 2)Gerald Van Baren2007-03-31-1/+101
| |_|_|/ |/| | | | | | | | | | | Modifications to the existing code to support the new fdt command.
* | | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xxWolfgang Denk2007-03-29-2/+22
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| * | | | Set Rev 2.x 86xx PIC in mixed mode.Haiying Wang2007-03-22-0/+20
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Prevent false interrupt from hanging Linux as MSR[EE] is set to enable interrupts by changing the PIC out of the default pass through mode into mixed mode. Signed-off-by: Haiying Wang <haiying.wang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
| * | | | Add support for 8641 Rev 2 silicon.Ed Swarthout2007-03-22-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Without this patch, I am unable to get to the prompt on rev 2 silicon. Only set ddrioovcr for rev1. Signed-off-by: Ed Swarthout<ed.swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | | | | Code cleanup / re-insert previous Copyright entries.Wolfgang Denk2007-03-22-1/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-blackfinWolfgang Denk2007-03-22-1420/+7647
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| * | | | | [Blackfin][PATCH] Add BF561 EZKIT board supportAubrey Li2007-03-20-0/+2865
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| * | | | | Merge http://www.denx.de/git/u-bootAubrey Li2007-03-19-1/+1
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| * | | | | | [Blackfin][PATCH] Add BF537 stamp board supportAubrey Li2007-03-19-0/+3621
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| * | | | | | [Blackfin][PATCH] minor cleanupAubrey Li2007-03-12-7/+7
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| * | | | | | [Blackfin][PATCH] Fix BUILD_DIR option of MAKEALL building issueAubrey Li2007-03-12-7/+11
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| * | | | | | [Blackfin][PATCH] code cleanupAubrey Li2007-03-12-115/+92
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| * | | | | | [Blackfin][PATCH] code cleanupAubrey Li2007-03-10-180/+177
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| * | | | | | [Blackfin]PATCH-1/2]: Remove obsolete blackfin port and add bf533 platform ↵Aubrey.Li2007-03-09-1454/+1217
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* | | | | | | Code cleanup. Update CHANGELOGWolfgang Denk2007-03-21-2/+2
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* | | | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-21-37/+323
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| * | | | | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-21-37/+323
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| | * | | | [PATCH] Add AMCC PPC405EZ supportStefan Roese2007-03-21-37/+323
| | | |_|/ | | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | SPC1920: fix small clock routing bugMarkus Klotzbuecher2007-03-21-3/+2
| |_|_|/ |/| | | | | | | | | | | Signed-off-by: Markus Klotzbuecher <mk@denx.de>
* | | | [PATCH] TQM8272: dont change the bits given from the HRCWHeiko Schocher2007-03-21-21/+5
|/ / / | | | | | | | | | | | | | | | | | | for the SIUMCR and BCR Register. Fix the calculation for the EEprom Size Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-1/+1
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| * | [PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUSMatthias Fuchs2007-03-08-1/+1
| | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-03-08-119/+498
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| * | | mpc83xx: Fix config of Arbiter, System Priority, and Clock ModeKumar Gala2007-03-02-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc83xx: update [local-]mac-address properties on UEC based devicesKim Phillips2007-03-02-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 8360 and 832x weren't updating their [local-]mac-address properties. This patch fixes that. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc83xx: write MAC address to mac-address and local-mac-addressTimur Tabi2007-03-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xxXie Xiaobo2007-03-02-61/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. it pass DDR/DDR2 compliance tests. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
| * | | mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDSXie Xiaobo2007-03-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8360E rev2.0 have new spridr,and PVR value, The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
| * | | mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDSXie Xiaobo2007-03-02-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8349E rev3.1 have new spridr,and PVR value, The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
| * | | mpc83xx: don't hang if watchdog configured on 8360, 832xKim Phillips2007-03-02-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | don't hang if watchdog configured on 8360, 832x The watchdog programming model is the same across all 83xx devices; make the code reflect that.
generated by cgit v1.1 at 2024-09-29 19:26:30 +0000