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* 83xx NAND boot: wait for LTESR[CC]Lepcha Suchit2008-10-17-0/+12
| | | | | | | | | | | | At least some revisions of the 8313, and possibly other chips, do not wait for all pages of the initial 4K NAND region to be loaded before beginning execution; thus, we wait for it before branching out of the first NAND page. This fixes warm reset problems when booting from NAND on 8313erdb. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* ppc4xx: PPC44x MQ initializationYuri Tikhonov2008-10-17-4/+6
| | | | | | | | | | | | | | | | | | | Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Comment from Stefan: This patch doesn't change the resulting value of the MQ registers. It explicitly sets/clears all bits to the desired state which better documents the resulting register value instead of relying on pre-set default values. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Revert "85xx: Using proper I2C source clock divider for MPC8544"Kumar Gala2008-10-17-2/+2
| | | | | | | | | | This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159. The fix introduced by this patch is not correct. The problem is that the documentation is not correct for the MPC8544 with regards to which bit in PORDEVSR2 is for the SEC_CFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: wait till UPM completes the write to arraySelvamuthukumar2008-10-14-3/+4
| | | | | | | | | | | Reference manual states that MxMR[MAD] increment is the indication of write to UPM array is complete. Honour that. Also, make the dummy write explicit. also fix the comment. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheNick Spence2008-10-13-4/+4
| | | | | | | | | | This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com>
* 86xx: remove redudant code with lib_ppc/interrupts.cKumar Gala2008-10-13-124/+7
| | | | | | | | | | For some reason we duplicated the majority of code in lib_ppc/interrupts.c Not know how that happened, but there is no good reason for it. Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-10-13-37/+57
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| * Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2008-10-12-29/+50
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| | * i.MX31: switch to CFG_HZ=1000Guennadi Liakhovetski2008-10-08-29/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to the standard CFG_HZ=1000 value, while at it, minor white-space cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads, provides 2% or 0.4% precision depending on the CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s boot-delay. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
| * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-12-7/+6
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| | * | 85xx: Using proper I2C source clock divider for MPC8544Wolfgang Grandegger2008-10-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
| | * | Fix the incorrect DDR clk freq reporting on 8536DSJason Jin2008-10-07-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| | * | 85xx: Remove setting of *cache-line-size in device treesKumar Gala2008-10-07-3/+0
| | |/ | | | | | | | | | | | | | | | | | | ePAPR says if the *cache-block-size is the same as *cache-line-size than we don't need the *cache-line-size property. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc83xx: spd_sdram: fix ddr sdram base address assignment bugAnton Vorontsov2008-09-24-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | The spd_dram code shifts the base address, then masks 20 bits, but forgets to shift the base address back. Fix this by just masking the base address correctly. Found this bug while trying to relocate a DDR memory at the base != 0. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR changeAdam Graham2008-10-08-0/+21
|/ | | | | | | | | | | | After changing SDRAM_CLKTR phase value rerun the memory preload initialization sequence (INITPLR) to reset and relock the memory DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects the phase relationship of the internal, to the PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Fix DPRAM memory leak when CFG_ALLOC_DPRAM is defined, whichWolfgang Denk2008-09-22-4/+6
| | | | | | | | eventually leads to a machine check. This change assures that DPRAM is allocated only once in that case. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de>
* sh: Add support watchdog for SH4A coreNobuhiro Iwamatsu2008-09-19-16/+37
| | | | | | | Add support watchdog for SH4A core (SH7763, SH7780 and SH7785). And fix some compile warning. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* Coding style cleanup, update CHANGELOGWolfgang Denk2008-09-13-16/+15
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-nand-flashWolfgang Denk2008-09-13-5/+76
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| * ARM DaVinci: Fix broken HW ECC for large page NAND.Hugo Villeneuve2008-09-10-5/+76
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Based on original patch by Bernard Blackham <bernard@largestprime.net> U-boot's HW ECC support for large page NAND on Davinci is completely broken. Some kernels, such as the 2.6.10 one supported by MontaVista for DaVinci, rely upon this broken behaviour as they share the same code for ECCs. In the existing scheme, error detection *might* work on large page, but error correction definitely does not. Small page ECC correction works, but the format is not compatible with the mainline git kernel. This patch adds ECC code that matches what is currently in the Davinci git repository (since NAND support was added in 2.6.24). This makes the ECC and OOB layout written by u-boot compatible with Linux for both small page and large page devices and fixes ECC correction for large page devices. The old behaviour can be restored by defining the macro CFG_DAVINCI_BROKEN_ECC, which is undefined by default. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com> Acked-by: Sergey Kubushyn <ksi@koi8.net> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | Merge branch 'Makefile-next' of git://git.denx.de/u-boot-armWolfgang Denk2008-09-12-3/+3
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| * | rename environment.c in env_embedded.c to reflect is functionalityJean-Christophe PLAGNIOL-VILLARD2008-09-10-2/+2
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | rename CFG_ENV_IS_IN_NVRAM in CONFIG_ENV_IS_IN_NVRAMJean-Christophe PLAGNIOL-VILLARD2008-09-10-1/+1
| |/ | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-09-12-4/+10
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| * | ppc4xx: Fix SDRAM inititialization of multiple 405 based board portsStefan Roese2008-09-12-4/+10
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem introdiced with patch bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by initdram()]. The boards affected are: - PCI405 - PPChameleonEVB - quad100hd - taihu - zeus Signed-off-by: Stefan Roese <sr@denx.de>
* | at91rm9200: fix errors with CONFIG_CMD_I2C_TREEJens Scharsig2008-09-12-0/+10
| | | | | | | | | | | | | | | | This patch prevents linker error on AT91RM9200 boards, if CONFIG_CMD_I2_TREE is set. It implements i2c_set_bus_speed and i2c_get_bus_speed as a dummy function. Signed-off-by: Jens Scharsig <esw@bus-elektronik.de>
* | ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.cHugo Villeneuve2008-09-12-20/+7
| | | | | | | | | | | | ARM DaVinci: Remove duplicate code in cpu/arm926ejs/davinci/dp83848.c Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
* | i.mx change get_timer(base) to return time since baseAndrew Dyer2008-09-12-1/+1
| | | | | | | | | | | | | | | | | | | | This patch changes get_timer() for i.MX to return the time since 'base' instead of the time since the counter was at zero. Symptom seen is flash timeout errors when erasing or programming a sector using the common cfi flash code. Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
* | i.MX use u-boot baud rate and don't assume UART master clockAndrew Dyer2008-09-12-15/+41
| | | | | | | | | | | | | | | | | | | | | | | | 1) Change the i.MX serial driver to use the baud rate set in the u-boot environment 2) don't assume a 16MHz value for PERCLK1 in baud rate calculations 3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write one to clear" like other status bits in the reg.) Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
* | arm920t fix constant error in start.SAndrew Dyer2008-09-12-2/+4
| | | | | | | | | | | | | | | | | | Code in cpu/arm920t/start.S will die with a compilation error if CONFIG_STACKSIZE + CFG_MALLOC_LEN works out to an invalid constant for the ARM sub instruction. Change the code so that each is subtracted independently to avoid the error. Signed-off-by: Andrew Dyer <adyer@righthandtech.com>
* | Set up SD/MMC OCR as comment describes. i.e. 3.2-3.4v.Adrian Filipi2008-09-12-2/+2
| | | | | | | | Signed-off-by: Adrian Filipi <adrian.filipi@eurotech.com>
* | i.MX31: Add reset_timer() and modify get_timer_masked().Magnus Lilja2008-09-12-4/+20
|/ | | | | | | | This patch adds the reset_timer() function (needed by nand_base.c) and modifies the get_timer_masked() to work in the same way as the omap24xx function. Signed-off-by: Magnus Lilja <lilja.magnus@gmail.com>
* Fix printf errors under -DDEBUGAndrew Klossner2008-09-09-7/+7
| | | | | | | | | | | | Fix printf format-string/arg mismatches under -DDEBUG. These warnings occur with DEBUG defined for a platform using cpu/mpc85xx. Users of other architectures can unearth similar problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right after "CFLAGS += $(call cc-option,-fno-stack-protector)". Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Ensure timebase is zero on secondary coresKumar Gala2008-09-09-0/+5
| | | | | | | The e500um says the timebase is volatile out of reset. To ensure TB sync works we need to make sure its zero. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.Sergei Poselenov2008-09-09-8/+7
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-09-09-74/+1504
|\ | | | | | | | | | | | | | | Conflicts: Makefile Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-09-08-3/+7
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| * | ppc4xx: Remove CONFIG_CS8952_PHY defineStefan Roese2008-09-08-2/+0
| | | | | | | | | | | | | | | | | | | | | | | | Since this define is only used on one board that was never really in production, removing this compile time option doesn't hurt and makes the code more readable. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix compilation warning for PIP405Stefan Roese2008-09-08-6/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a compilation warning for the PIP405 board. It moves the #ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't occur anymore. I am a little unsure if this #ifdef is at the correct place now or if it could be removed completely. This needs to get tested on the PIP405 board. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix compilation warning for canyonlands & glacierStefan Roese2008-09-08-7/+3
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Add support for GPCS, SGMII and M88E1112 PHYVictor Gallardo2008-09-05-5/+195
| | | | | | | | | | | | | | | | | | | | | | | | This patch adds GPCS, SGMII and M88E1112 PHY support for the AMCC PPC460GT/EX processors. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routinesAdam Graham2008-09-05-63/+98
| | | | | | | | | | | | | | | Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: IBM Memory Controller DDR autocalibration routinesAdam Graham2008-09-05-0/+1212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alternate SDRAM DDR autocalibration routine that can be generically used for any PPC4xx chips that have the IBM SDRAM Controller core allowing for support of more DIMM/memory chip vendors and gets the DDR autocalibration values which give the best read latency performance (SDRAM0_RDCC.[RDSS]). Two alternate SDRAM DDR autocalibration algoritm are provided in this patch, "Method_A" and "Method_B". DDR autocalibration Method_A scans the full range of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a lot longer to run than Method_B. Method_B executes in the same amount of time as the currently existing DDR autocalibration routine, i.e. 1 second or so. Normally Method_B is used and it is set as the default method. The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_RQDC.[RQFD] 2) SDRAM0_RFDC.[RFFD] This alternate PPC4xx DDR autocalibration code calibrates the following IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_WRDTR.[WDTR] 2) SDRAM0_CLKTR.[CKTR] 3) SDRAM0_RQDC.[RQFD] 4) SDRAM0_RFDC.[RFFD] and will also use the calibrated settings of the above four registers that produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS] register.[bit-field]. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | ARM: fix warning: target CPU does not support interworkingSergei Poselenov2008-09-09-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes warnings like this: start.S:0: warning: target CPU does not support interworking which come from some ARM cross compilers and are caused by hard-coded (with "--with-cpu=arm9" configuration option) ARM targets (which support ARM Thumb instructions), while the ARM target selected from the command line (with "-march=armv4") doesn't support Thumb instructions. This warning is issued by the compiler regardless of the real use of the Thumb instructions in code. To fix this problem, we use options according to compiler version being used. Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | ARM: Use do_div() instead of division for "long long".Sergei Poselenov2008-09-09-1/+4
| |/ |/| | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Fix compiler warning in mpc8xxx ddr codeKumar Gala2008-09-07-2/+4
| | | | | | | | | | | | | | | | | | | | | | ctrl_regs.c: In function 'compute_fsl_memctl_config_regs': ctrl_regs.c:523: warning: 'caslat' may be used uninitialized in this function ctrl_regs.c:523: note: 'caslat' was declared here Add a warning in DDR1 case if cas_latency isn't a value we know about. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | rtc: allow rtc_set to return an error and use it in cmd_dateJean-Christophe PLAGNIOL-VILLARD2008-09-07-1/+3
|/ | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2008-09-03-28/+183
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| * mpc83xx: clean up cache operations and unlock_ram_in_cache() functionsNick Spence2008-09-03-21/+30
| | | | | | | | | | | | | | | | | | Cleans up some latent issues with the data cache control so that dcache_enable() and dcache_disable() will work reliably (after unlock_ram_in_cache() has been called) Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc83xx: Store and display Arbiter Event Register valuesNick Spence2008-09-03-1/+146
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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