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* Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-08-14-99/+296
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| * Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-08-14-3083/+8470
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| * | Coding style cleanupStefan Roese2007-08-14-2/+2
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | Merge with /home/stefan/git/u-boot/zeusStefan Roese2007-08-14-30/+67
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| | * | ppc4xx: Add initial Zeus (PPC405EP) board supportStefan Roese2007-08-14-42/+35
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| | * | ppc4xx: Add support for AMCC 405EP Taihu boardJohn Otken2007-07-26-1/+45
| | | | | | | | | | | | | | | | Signed-off-by: John Otken <john@softadvances.com>
| * | | ppc4xx: Fix problem in PLL clock calculationStefan Roese2007-08-13-18/+24
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch was originall provided by David Mitchell <dmitchell@amcc.com> and fixes a bug in the PLL clock calculation. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Code cleanupStefan Roese2007-08-02-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | [ppc440SPe] Graceful recovery from machine check during PCIe configurationGrzegorz Bernacki2007-08-02-9/+57
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | During config transactions on the PCIe bus an attempt to scan for a non-existent device can lead to a machine check exception with certain peripheral devices. In order to avoid crashing in such scenarios the instrumented versions of the config cycle read routines are introduced, so the exceptions fixups framework can gracefully recover. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Acked-by: Rafal Jaworowski <raj@semihalf.com>
| * | | [ppc4xx] Separate settings for PCIe bus numbering on 440SPe rev.ARafal Jaworowski2007-08-02-3/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This brings back separate settings for PCIe bus numbers depending on chip revision, which got eliminated in 2b393b0f0af8402ef43b25c1968bfd29714ddffa commit. 440SPe rev. A does NOT work properly with the same settings as for the rev. B (no devices are seen on the bus during enumeration). Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
| * | | ppc4xx: Update AMCC Bamboo 440EP supportEugene OBrien2007-07-31-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Changed storage type of cfg_simulate_spd_eeprom to const Changed storage type of gpio_tab to stack storage (Cannot access global data declarations in .bss until afer code relocation) Improved SDRAM tests to catch problems where data is not uniquely addressable (e.g. incorrectly programmed SDRAM row or columns) Added CONFIG_PROG_SDRAM_TLB to support Bamboo SIMM/DIMM modules Fixed AM29LV320DT (OpCode Flash) sector map Signed-off-by: Eugene OBrien <eugene.obrien@advantechamt.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Only print ECC related info when the error bis are setStefan Roese2007-07-30-14/+24
| |/ / | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Fix bug with default GPIO output valueStefan Roese2007-07-20-2/+2
| | | | | | | | | | | | | | | | | | | | | As spotted by Matthias Fuchs, the default output values for all GPIO1 outputs were not setup correctly. This patch fixes this issue. Signed-off-by: Stefan Roese <sr@denx.de>
| * | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-07-16-8/+15
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| * | | ppc4xx: Code cleanupStefan Roese2007-07-16-1/+0
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Add new weak functions to support boardspecific DDR2 configurationStefan Roese2007-07-16-14/+44
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better support non default, boardspecific DDR(2) controller configuration. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Add remove_tlb() function to remove a mem area from TLB setupStefan Roese2007-07-16-1/+61
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | ppc4xx: Change receive buffer handling in the 4xx emac driverStefan Roese2007-07-12-3/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This change fixes a bug in the receive buffer handling, that could lead to problems upon high network traffic (broadcasts...). Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Coding style cleanup. Update CHANGELOG.Wolfgang Denk2007-08-14-2/+0
| | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | | | Add the files.Peter Pearse2007-08-14-0/+153
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* | | | Add MACH_TYPE records for several AT91 boards.Peter Pearse2007-08-14-8/+98
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | Merge to two at45.c files into a common file, split to at45.c and spi.c Fix spelling error in DM9161 PHY Support. Initialize at91rm9200 board (and set LED). Add PIO control for at91rm9200dk LEDs and Mux. Change dataflash partition boundaries to be compatible with Linux 2.6. Signed-off-by: Peter Pearse <peter.pearse@arm.com> Signed-off-by: Ulf Samuelsson <ulf@atmel.com>
* | | 85xxCDS: Add make targets for legacy systems.Randy Vinson2007-08-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson <rvinson@mvista.com>
* | | Add support for UEC to 8568Andy Fleming2007-08-14-2/+142
| | | | | | | | | | | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | Empirically set cpo and clk_adjust for mpc85xx DDR2 supportHaiying Wang2007-08-14-5/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch is against u-boot-mpc85xx.git of www.denx.com Setting cpo to 0x9 for frequencies higher than 333MHz is verified on both MPC8548CDS board and MPC8568MDS board, especially for supporting 533MHz DDR2. Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for DDR2 on all current board versions especially ver 1.92 or later to bring up. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* | | Use an absolute address when jumping out of 4k boot pageKumar Gala2007-08-14-29/+24
| | | | | | | | | | | | | | | | | | | | | On e500 when we leave the 4k boot page we should use an absolute address since we don't know where the board code may want us to be really running at. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | MPC85xx BA bits not set for 3-bit bank address DIMMAndy Fleming2007-08-14-1/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current implementation does not set the number of bank address bits (BA) in the processor. The default assumes 2 logical bank bits. This works fine for a DIMM that uses devices with 4 internal banks (SPD byte17 = 0x4) but needs to be set appropriately for a DIMM that uses devices with 8 internal banks (SPD byte17 = 0x8). Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
* | | Fix minor 85xx warningsAndy Fleming2007-08-14-1/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming <afleming@freescale.com>
* | | 85xx start.S cleanup and exception supportAndy Fleming2007-08-14-298/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | From: Ed Swarthout <Ed.Swarthout@freescale.com> Support external interrupts from platform to eliminate system hangs. Define CONFIG_INTERRUPTS board configure option to enable. Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. Remove extra cpu initialization redundant with hardware initialization. Whitespace cleanup. Define and use _START_OFFSET consistent with other processors using ppc_asm.tmpl Move additional code from .text to boot page to make room for exception vectors at start of image. Handle Machine Check, External and Critical exceptions. Fix e500 machine check error determination in traps.c TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* | | 85xx allow debugger to configure ddr.Ed Swarthout2007-08-14-3/+45
| | | | | | | | | | | | | | | | | | | | | Only check for mpc8548 rev 1 when compiled for 8548. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* | | mpc85xx L2 cache reporting and SRAM relocation option.Ed Swarthout2007-08-14-18/+47
| | | | | | | | | | | | | | | | | | | | | | | | Allow debugger to override flash cs0/cs1 settings to enable alternate boot regions Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc86xxWolfgang Denk2007-08-13-97/+51
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| * \ \ Merge commit 'remotes/wd/master'Jon Loeliger2007-08-13-13/+2699
| |\ \ \ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: MAKEALL With any luck, this is the last MAKEALL merge conflict!
| * | | | cpu/86xx fixes.Jon Loeliger2007-08-10-97/+51
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove rev 1 fixes. Always set PICGCR_MODE. Enable machine check and provide board config option to set and handle SoC error interrupts. Include MSSSR0 in error message. Isolate a RAMBOOT bit of code with #ifdef CFG_RAMBOOT. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* | | | | atmel_mci: Fix data timeout valueHaavard Skinnemoen2007-08-13-0/+59
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Calculate the data timeout based on values from the CSD instead of just using a hardcoded DTOR value. This is a backport of a similar fix in BSP 2.0, with one additional fix: the DTOCYC value is rounded up instead of down. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* | | | | AVR32: Include <div64.h> instead of <asm/div64.h>Haavard Skinnemoen2007-08-13-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | include/asm-avr32/div64.h was recently moved to include/div64.h, but cpu/at32ap/interrupts.c wasn't properly updated (an earlier version of the patch was merged perhaps?) This patch updates cpu/at32ap/interrupts.c so that the avr32 port compiles again. Signed-off-by: Haavard Skinnemoen <hskinnemoen@atmel.com>
* | | | | Merge commit 'upstream/master'Haavard Skinnemoen2007-08-13-3035/+8385
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| * | | | Minor alignment of output, 2nd try.Wolfgang Denk2007-08-12-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Also update CHANGELOG Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | Minor alignment of outputWolfgang Denk2007-08-12-2/+2
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | Clean up some remaining CFG_CMD_ -> CONFIG_CMD_ issues.Wolfgang Denk2007-08-12-11/+11
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * | | | mpc83xx: Suppress the warning 'burstlen'Dave Liu2007-08-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | suppress the warning 'burstlen' of spd_sdram. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | | | Conding style cleanupStefan Roese2007-08-10-3/+1
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-08-10-57/+552
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| | * | | mpc83xx: Consolidate the ECC support of 83xxDave Liu2007-08-10-1/+391
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Remove the duplicated source code of ecc command on the <board>.c, for reused, move these code to cpu/mpc83xx directory. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | | mpc83xx: Correct the burst length for DDR2 with 32 bitsDave Liu2007-08-10-3/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The burst length should be 4 for DDR2 with 32 bits bus Signed-off-by: Dave Liu <daveliu@freescale.com>
| | * | | mpc83xx: fixup generic pci for libfdtKim Phillips2007-08-10-1/+35
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | add libfdt support to the generic 83xx pci code Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | | mpc83xx: fix 8360 and cpu functions to update fdt being passedKim Phillips2007-08-10-18/+18
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | ..and not the global fdt. Rename local fdt vars to blob so as not to be confused with the global var with the same three-letter name. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | | mpc83xx: Fix errors when CONFIG_OF_LIBFDT is enabledJerry Van Baren2007-08-10-28/+46
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Several node strings were not correct (trailing slashes and properties in the strings) Added setting of the timebase-frequency. Improved error messages and use debug() instead of printf(). Signed-off-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | | mpc83xx: Replace fdt_node_offset() with fdt_find_node_by_path().Jerry Van Baren2007-08-10-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The new name matches more closely the kernel's name, which is also a much better description. These are the mpc83xx changes made necessary by the function name change. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com> Acked-by: Gerald Van Baren <vanbaren@cideas.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | | mpc83xx: Add support for the display of reset statusDave Liu2007-08-10-0/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 83xx processor family has many reset sources, such as power on reset, software hard reset, software soft reset, JTAG, bus monitor, software watchdog, check stop reset, external hard reset, external software reset. sometimes, to figure out the fault of system, we need to know the cause of reset early before the prompt of u-boot present. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * | | Update SCCR programming in cpu_init_f() to support all 83xx processorsTimur Tabi2007-08-10-2/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Update the cpu_init_f() function in cpu/mpc83xx/cpu_init.c to program the bitfields for all 83xx processors. The code to update some bitfields was compiled only on some processors. Now, the bitfields are programmed as long as the corresponding CFG_SCCR option is defined in the board header file. This means that the board header file should not define any CFG_SCCR macros for bitfields that don't exist on that processor, otherwise the SCCR will be programmed incorrectly. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
generated by cgit v1.1 at 2024-11-17 06:48:34 +0000