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* ColdFire: Fix compilation errorTsiChung Liew2008-11-03-9/+9
| | | | | | | The error was caused by the change for strmhz() in cpu.c. A few of them were one extra close parenthesis. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Add MCF5301x CPU and M53017EVB supportTsiChung Liew2008-11-03-49/+304
| | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Add SBF support for M52277EVBTsiChung Liew2008-11-03-17/+541
| | | | | | Add serial boot support Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Relocate FEC's GPIO and mii functions protocolsTsiChung Liew2008-11-03-3/+185
| | | | | | | Place FEC pin assignments in cpu_init.c from platform's mii.c Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* ColdFire: Modules header files cleanupTsiChung Liew2008-11-03-191/+80
| | | | | | | | | | | | Consolidate ATA, ePORT, QSPI, FlexCan, PWM, RNG, MDHA, SKHA, INTC, and FlexBus structures and definitions in immap_5xxx.h to more unify modules header files. Append DSPI support for m547x_8x. SSI cleanup. Remove USB Host structure from immap_539.h. Apply changes to use FlexBus structures in mcf52x2's cpu_init.c and platform configuration files. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-blackfinWolfgang Denk2008-11-01-305/+128
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| * Blackfin: fix up UART status bit handlingMike Frysinger2008-10-23-12/+60
| | | | | | | | | | | | | | | | Some Blackfin UARTs are read-to-clear while others are write-to-clear. This can cause problems when we poll the LSR and then later try and handle any errors detected. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: small cpu init optimization while setting interrupt maskMike Frysinger2008-10-23-5/+2
| | | | | | | | | | | | | | Use the sti instruction to set the initial interrupt mask rather than banging on the core IMASK MMR to save both space and time. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: set initial stack correctly according to Blackfin ABIMike Frysinger2008-10-23-3/+3
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: make baud calculation more accurateMike Frysinger2008-10-23-4/+4
| | | | | | | | | | | | | | | | We should use the algorithm in the Linux kernel so that the UART divisor calculation is more accurate. It also fixes problems on some picky UARTs that have sampling anomalies. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: decode hwerrcause/excause when crashingMike Frysinger2008-10-23-2/+40
| | | | | | | | | | | | Having to decode hwerrcause/excause values is a pain, so automate it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: fix register dump messagesMike Frysinger2008-10-23-1/+5
| | | | | | | | | | | | Make sure we report RETI/IPEND correctly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: don't bother displaying reboot msg when crashingMike Frysinger2008-10-23-5/+1
| | | | | | | | | | | | | | The hang function already tells you to reboot, so no point in showing it twice. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: enable support for nested interruptsMike Frysinger2008-10-23-4/+10
| | | | | | | | | | | | | | During cpu init, make sure we initialize the CEC properly so that interrupts can fire and be handled while U-Boot is running. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: drop unused cache flush codeMike Frysinger2008-10-23-231/+1
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: unify cache handling codeMike Frysinger2008-10-23-35/+0
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
| * Blackfin: only enable hardware error irq by defaultMike Frysinger2008-10-23-3/+2
| | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | 74xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheDave Liu2008-10-31-4/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The patch is following the commit 392438406041415fe64ab8748ec5ab5ad01d1cf7 mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com> also, the r2 is used as global data pointer. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2008-10-30-1/+1
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| * | mpc83xx pci: Round up memory size in inbound window.Scott Wood2008-10-30-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | The current calculation will fail to cover all memory if its size is not a power of two. Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | Merge branch 'master' of git://git.denx.de/u-boot-mpc86xxWolfgang Denk2008-10-30-16/+4
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| * | | 86xx: remove the redundant r2 global data pointer saveDave Liu2008-10-30-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The commit 67256678f00c09b0a7f19e862e5c1847553d31bc add the another global data pointer save, but in fact the global data pointer will be initialized in the board_init_r, so remove it such as the 85xx/83xx family. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
| * | | 86xx: remove the unused code for 86xx familyDave Liu2008-10-30-14/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I believe these code was copied from 74xx family, but for 86xx, it is unused. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
| * | | 86xx: Move the clear_tlbs before MMU turn onDave Liu2008-10-30-1/+4
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | We must invalidate TLBs before MMU turn on, but currently the code is not, if there are some stale TLB entry valid in the TLBs, it will cause strange issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* | | Make Freescale local bus registers available for both 83xx and 85xx.Haiying Wang2008-10-29-1/+1
|/ / | | | | | | | | | | | | | | | | | | | | | | | | - Rename lbus83xx_t to fsl_lbus_t and move it to asm/fsl_lbc.h so that it can be shared by both 83xx and 85xx - Remove lbus83xx_t and replace it with fsl_lbus_t in all 83xx boards files which use lbus83xx_t. - Move FMR, FIR, FCR, FPAR, LTESR from mpc83xx.h to asm/fsl_lbc.h so that 85xx can share them. Signed-off-by: Jason Jin <Jason.Jin@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* | i386: Renamed show_boot_progress in assembler codeGraeme Russ2008-10-28-10/+10
| | | | | | | | | | | | | | Renamed show_boot_progress in assembler init phase to show_boot_progress_asm to avoid link conflicts with C version Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-27-5/+22
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| * | 85xx: Fix the incorrect register used for DDR erratum1Dave Liu2008-10-24-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | 85xx: Add basic e500mc core supportKumar Gala2008-10-24-0/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic numberKumar Gala2008-10-24-2/+2
| |/ | | | | | | | | | | | | Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc4xx: Generic architecture for xilinx ppc405(v3)Ricardo Ribalda Delgado2008-10-24-1/+2
|/ | | | | | | | | | | | | | | | | As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
* mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig functionRichard Retanubun2008-10-21-5/+0
| | | | | | | | This is done to allow other 83XX based platforms which also have UPM (e.g. 8360) to configure and use their UPM in u-boot. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: serdes: add forgotten shifts for rfcksAnton Vorontsov2008-10-21-1/+1
| | | | | | | | | | The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-36/+99
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| * ppc4xx: Correctly setup ranges property in ebc nodeStefan Roese2008-10-21-17/+28
| | | | | | | | | | | | | | | | Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add routine to retrieve CPU numberAdam Graham2008-10-21-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add static support for 44x IBM SDRAM ControllerAdam Graham2008-10-21-18/+53
| | | | | | | | | | | | | | | | | | | | This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-12/+12
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Use strmhz() to format clock frequenciesWolfgang Denk2008-10-21-73/+99
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge git://git.denx.de/u-boot into x1Markus Klotzbuecher2008-10-21-3657/+3816
|\ \ | |/ | | | | | | | | Conflicts: drivers/usb/usb_ohci.c
| * Merge 'next' branchWolfgang Denk2008-10-18-3476/+3673
| |\ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * 85xx if NUM_CPUS>1, print cpu numberEd Swarthout2008-10-18-0/+5
| | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * Have u-boot pass stashing parameters into device treeAndy Fleming2008-10-18-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some cores don't support ethernet stashing at all, and some instances have errata. Adds 3 properties to gianfar nodes which support stashing. For now, just add this support to 85xx SoCs. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
| | | | | | | | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Check DDR interleaving modeHaiying Wang2008-10-18-5/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Check DDR interleaving mode from environment by reading memctl_intlv_ctl and ba_intlv_ctl. * Print DDR interleaving mode information * Add doc/README.fsl-ddr to describe the interleaving setting Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-87/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-12/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * 85xx: Export invalidate_{i,d}cache and add flush_dcacheKumar Gala2008-10-18-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-3365/+3365
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| | * 74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx versionKumar Gala2008-10-18-10/+10
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-17 04:49:51 +0000