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* nios2: Move cpu/nios2/* to arch/nios2/cpu/*Peter Tyser2010-04-13-1592/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* nios: Move cpu/nios/* to arch/nios/cpu/*Peter Tyser2010-04-13-2191/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* sparc: Move cpu/leon[23] to arch/sparc/cpu/leon[23]Peter Tyser2010-04-13-6697/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* i386: Move cpu/i386/* to arch/i386/cpu/*Peter Tyser2010-04-13-2643/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* microblaze: Move cpu/microblaze/* to arch/microblaze/cpu/*Peter Tyser2010-04-13-824/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* avr32: Move cpu/at32ap/* to arch/avr32/cpu/*Peter Tyser2010-04-13-2078/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* mips: Move cpu/mips/* to arch/mips/cpu/*Peter Tyser2010-04-13-4305/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* blackfin: Move cpu/blackfin/* to arch/blackfin/cpu/*Peter Tyser2010-04-13-2757/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* m68k: Move cpu/$CPU to arch/m68k/cpu/$CPUPeter Tyser2010-04-13-7401/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* arm: Move cpu/$CPU to arch/arm/cpu/$CPUPeter Tyser2010-04-13-101616/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* sh: Move cpu/$CPU to arch/sh/cpu/$CPUPeter Tyser2010-04-13-1638/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-13-82264/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>"Peter Tyser2010-04-13-1/+1
| | | | | | | | | | The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Rename lib_generic/ to lib/Peter Tyser2010-04-13-1/+1
| | | | | | | | Now that the other architecture-specific lib directories have been moved out of the top-level directory there's not much reason to have the '_generic' suffix on the common lib directory. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Move lib_$ARCH directories to arch/$ARCH/libPeter Tyser2010-04-13-2/+2
| | | | | | | | | Also move lib_$ARCH/config.mk to arch/$ARCH/config.mk This change is intended to clean up the top-level directory structure and more closely mimic Linux's directory organization. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-04-08-23/+88
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| * fsl: improve the PIXIS code and fix a few bugsTimur Tabi2010-04-07-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. Delete pixis.h, because none of the exported functions were actually being used by any other file. Make all of the functions in pixis.c 'static'. Remove "#include pixis.h" from every file that has it. Remove some unnecessary #includes. Make 'pixis_base' into a macro, so that we don't need to define it in every function. Add "while(1);" loops at the end of functions that reset the board, so that execution doesn't continue while the reset is in progress. Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where appropriate. Replace ulong/uint with their spelled-out equivalents. Remove unnecessary typecasts, changing the types of some variables if necessary. Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make it easier for specific boards to support variations in the PIXIS registers sets. No current boards appears to need this feature. Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. Apparently, "pixis_reset altbank" has never worked on this board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greaterSandeep Gopalpet2010-04-07-0/+14
| | | | | | | | | | | | | | The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
| * 85xx: Added various P1012/P1013/P1021/P1022 definesKumar Gala2010-04-07-4/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Add defines for BUCSR bits to make code more readableKumar Gala2010-04-07-5/+7
| | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * fsl-ddr: change the default burst mode for DDR3Dave Liu2010-04-07-4/+10
| | | | | | | | | | | | | | For 64B cacheline SoC, set the fixed 8-beat burst len, for 32B cacheline SoC, set the On-The-Fly as default. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * fsl-ddr: Fix the turnaround timing for TIMING_CFG_4Dave Liu2010-04-07-9/+17
| | | | | | | | | | | | | | | | | | | | Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu <daveliu@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-i2cWolfgang Denk2010-04-08-440/+0
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| * | i2c: Move PPC4xx I2C driver into drivers/i2c directoryStefan Roese2010-04-06-440/+0
| |/ | | | | | | | | | | | | | | This patch moves the PPC4xx specific I2C device driver into the I2C drivers directory. All 4xx config headers are updated to include this driver. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2010-04-08-43/+248
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| * | using AT91_PMC_MCKR_MDIV_ instead of LEGACY one in at91/clock.cAsen Dimov2010-04-03-1/+2
| | | | | | | | | | | | Signed-off-by: Asen Dimov <dimov@ronetix.at>
| * | Nomadik: fix reset_timer()Alessandro Rubini2010-04-03-3/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Previous code was failing when reading back the timer less than 400us after resetting it. This lead nand operations to incorrectly timeout any now and then. Moreover, writing the load register isn't immediately reflected in the value register. We must wait for a clock edge, so read_timer now waits for the value to change at least once, otherwise nand operation would timeout anyways (though less frequently). Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stericsson.com>
| * | ep93xx timer: refactoringMatthias Kaehlcke2010-04-03-28/+24
| | | | | | | | | | | | | | | | | | | | | ep93xx timer: Simplified the timer code by eliminating clk_to_systicks() and performing (almost) all manipulation of the timer structure in read_timer() Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
| * | ep93xx timer: Rename struct timer_reg pointersMatthias Kaehlcke2010-04-03-6/+6
| | | | | | | | | | | | | | | | | | | | | ep93xx timer: Renamed pointers to struct timer_regs from name 'timer' to 'timer_regs' in order to avoid confusion with the global variable 'timer' Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
| * | S5PC100: Function to configure the SROMC registers.Naveen Krishna CH2010-04-03-0/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | Nand Flash, Ethernet, other features might need to configure the SROMC registers accordingly. The config_sromc() functions helps with this. Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | s5pc1xx: support the GPIO interfaceMinkyu Kang2010-04-03-0/+144
| | | | | | | | | | | | | | | | | | This patch adds support the GPIO interface Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | s3c64xx: Add ifdef at the S3C64XX only codesJoonyoung Shim2010-04-03-0/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | The s3c6400.h file is only for S3C64XX cpu and the pheripheral port address(0x70000000 - 0x7fffffff) exists at only S3C64XX cpu, so they should be included by only S3C64XX cpu. Signed-off-by: Joonyoung Shim <jy0922.shim@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
| * | S5PC100: Moves the Macros to a common header fileNaveen Krishna CH2010-04-03-6/+1
| |/ | | | | | | | | | | | | | | | | | | | | The get_pll_clk(int) API returns the PLL frequency based on the (int) argument which is defined locally in clock.c Moving that #define to common header file (clk.h) would be helpful when using the API from other files. Signed-off-by: Naveen Krishna Ch <ch.naveen@samsung.com> Signed-off-by: Minkyu Kang <mk7.kang@samsung.com>
* | nios2: Reload timer count in reset_timer()Scott McNutt2010-04-02-0/+33
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When the timestamp is incremented via interrupt and the interrupt period is greater than 1 msec, successive calls to get_timer() can produce inaccurate timing since the interrupts are asynchronous to the timing loop. For example, with an interrupt period of 10 msec two successive calls to get_timer() could indicate an elapsed time of 10 msec after only several hundred usecs -- depending on when the next interrupt actually occurs. This behavior can cause reliability issues with components such as CFI and NAND. This can be remedied by calling reset_timer() prior to establishing the base timestamp with get_timer(0), provided reset_timer() resets the hardware timer (rather than simply resetting only the timestamp). This has the effect of synchronizing the interrupts (and the advance of the timestamp) with the timing loop. Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: Fix outx/writex parameter order in io.hScott McNutt2010-04-02-11/+11
| | | | | | | | | | | | | | | | | | The outx/writex macros were using writex(addr, val) rather than the standard writex(val, addr), resulting in incompatibilty with architecture independent components. This change set uses standard parameter order. Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: Add support for EPCS16 and EPCS64 configuration devices.Scott McNutt2010-04-02-4/+8
| | | | | | | | Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* | nios2: Move serial drivers to individual files in drivers/serialScott McNutt2010-04-02-310/+1
|/ | | | | | | | The standard Altera UART & JTAG UART as well as the OpenCores YANU driver are now in individual files in drivers/serial rather than a single file uner cpu/nios2. Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* Merge branch 'next'Wolfgang Denk2010-04-01-1112/+200
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| * Merge remote branch 'origin/master' into nextWolfgang Denk2010-03-29-5/+60
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| * | ColdFire: Cache update for all platformsTsiChung Liew2010-03-24-597/+32
| | | | | | | | | | | | | | | | | | | | | The CF will call cache functions in lib_m68/cache.c and the cache settings are defined in platform configuration file. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | ColdFire: Misc update for M53017TsiChung Liew2010-03-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update DRAM control and SRAM control register setting. Update cache setting where size does not write to proper region. Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * | ColdFire: Add CPU compile flag for mcf5301x and mcf532xTsiChung Liew2010-03-24-0/+12
| | | | | | | | | | | | | | | | | | Add CPU compile flag -mcpu=53015 in cpu/config.mk Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | ColdFire: Relocate vector table - mcf5445xTsiChung Liew2010-03-24-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer ColdFire processors family boot from address 0 instead of 0xFFnn_nnnn. When the boot flash base chip select is set at new location instead of 0, an un-predictable error will occur if there is an vector being trigger and refer it to an invalid address or the vector table handler is not existed at address 0. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | ColdFire: Update processors' serial port configurationTsiChung Liew2010-03-24-51/+105
| | | | | | | | | | | | | | | | | | | | | Provide parameter passing to uart_port_config(). Update port configuration - un-mask it before enable the bits. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | ColdFire: Correct bit definitionTsiChung Liew2010-03-24-22/+22
| | | | | | | | | | | | | | | | | | | | | Use correct definition for _MASK and _UNMASK. It was combined in the previous used and causes confusion. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | Adding EP2500 MCF5282 board [PATCH]Michael Durrant2010-03-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mercury-EP2500.patch - added Mercury's EP2500 board uses the mcf5282 processor CREDITS.patch Signed-off-by: David Wu <davidwu@arcturusnetworks.com> Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com>
| * | Merge remote branch 'origin/master' into nextWolfgang Denk2010-03-22-18/+13
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| * \ \ Merge remote branch 'origin/master' into nextWolfgang Denk2010-03-21-2/+2
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| * | | | nios2: Added support to YANU UARTRenato Andreola2010-03-21-1/+167
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | | mpc5xxx: Remove all references to MGT5100Detlev Zundel2010-03-21-443/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not support a processor that never reached a real customer. Signed-off-by: Detlev Zundel <dzu@denx.de>
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