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* Coldfire: Fix half-baud UART by adding M5271 to Coldfire v2 core listRichard Retanubun2009-02-06-1/+2
| | | | | | | | | Added the CONFIG_M5271 to the list of Coldfire V2 processor. This was causing the bus clock (not CPU clock) to be declared twice as fast as it actually is. This causes UARTS to operate at half the specified baudrate. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com>
* Blackfin: rewrite cache handling functionsMike Frysinger2009-02-02-46/+72
| | | | | | | Take the cache flush functions from the kernel as they use hardware loops in order to get optimal performance. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: enable --gc-sectionsMike Frysinger2009-02-02-0/+1
| | | | | | | Start building all Blackfin boards with -ffunction-sections/-fdata-sections and linking with --gc-sections. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: dont check baud if it wont actually get usedMike Frysinger2009-02-02-1/+5
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2009-02-01-0/+3169
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| * Initial support for Nomadik 8815 development boardAlessandro Rubini2009-01-24-0/+254
| | | | | | | | | | | | | | | | | | | | | | | | | | The NMDK8815 board is distributed by ST Microelectornics. Other (proprietary) code must be run to unlock the CPU before U-Boot runs. doc/README.nmdk8815 outlines the boot sequence. This is the initial port, with basic infrastructure and a working serial port. Signed-off-by: Alessandro Rubini <rubini@unipv.it> Acked-by: Andrea Gallo <andrea.gallo@stnwireless.com> Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * OMAP3: Add common board, interrupt and system infoDirk Behme2009-01-24-0/+895
| | | | | | | | | | | | Add common board, interrupt and system info code. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
| * OMAP3: Add common clock, memory and low level codeDirk Behme2009-01-24-0/+1098
| | | | | | | | | | | | Add common clock, memory and low level code Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
| * OMAP3: Add common cpu and start codeDirk Behme2009-01-24-0/+922
| | | | | | | | | | | | Add common cpu and start code. Signed-off-by: Dirk Behme <dirk.behme@googlemail.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-netWolfgang Denk2009-02-01-12/+57
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| * | mgcoge make ether_scc.c work with CONFIG_NET_MULTIGary Jennejohn2009-01-24-12/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change is needed for mgcoge because it uses two ethernet drivers. Add a check for the presence of the PIGGY board on mgcoge. Without this board networking cannot work and the initialization must be aborted. Only allocate rtx once to prevent DPRAM exhaustion. Initialize ether_scc.c and the keymile-specific HDLC driver (to be added soon) in eth.c. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | sh: sh_eth: Change new network APINobuhiro Iwamatsu2009-01-24-0/+8
| |/ | | | | | | | | | | | | sh_eth used old network API. This patch changed new API. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | ixp: move serial to drivers/serialJean-Christophe PLAGNIOL-VILLARD2009-01-31-126/+0
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: move pci init in arm/board instead of cpuJean-Christophe PLAGNIOL-VILLARD2009-01-31-3/+0
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: move pci drivers to drivers/pciJean-Christophe PLAGNIOL-VILLARD2009-01-31-572/+0
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2009-01-31-10/+10
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: add missing os defineJean-Christophe PLAGNIOL-VILLARD2009-01-31-1/+1
| | | | | | | | | | | | need by arm-elf toolchains and no impact on the arm-linux one Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp: remove the option to include the MicrocodeJean-Christophe PLAGNIOL-VILLARD2009-01-31-13/+8
| | | | | | | | | | | | | | instead the board will have to load it from flash or ram which will be specified by npe_ucode env var Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | ixp/npe: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2009-01-30-10/+6
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-usbWolfgang Denk2009-01-28-7/+3
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| * | usb.h: use standard __LITTLE_ENDIAN from Linux headersMike Frysinger2009-01-28-7/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | Rather than forcing people to define a custom "LITTLEENDIAN", just use the __LITTLE_ENDIAN one from the Linux byteorder headers that every arch is already setting up. Signed-off-by: Mike Frysinger <vapier@gentoo.org> Signed-off-by: Remy Bohmer <linux@bohmer.net>
* | | Blackfin: fixup misc warnings such as printf's and missing castsMike Frysinger2009-01-28-10/+11
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: allow serial console to be disabledMike Frysinger2009-01-28-0/+8
| | | | | | | | | | | | | | | | | | | | | Some devices have no UART device pulled out, so allow people to disable the driver completely in favor of other methods (like JTAG-console). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: support console-over-JTAGMike Frysinger2009-01-28-4/+130
| | | | | | | | | | | | | | | | | | | | | The Blackfin JTAG has the ability to pass data via a back-channel without halting the processor. Utilize that channel to emulate a console. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: handle new anomalies with resetMike Frysinger2009-01-28-5/+15
| | | | | | | | | | | | | | | | | | Workaround fun new anomalies related to software reset of the processor. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: pass RETX to LinuxMike Frysinger2009-01-28-0/+6
| | | | | | | | | | | | | | | | | | | | | Make sure we save the value of RETX at power on and then pass it on to the kernel so that it can nicely debug a "double-fault-caused-a-reset" crash. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: clarify relocation comment during initMike Frysinger2009-01-28-3/+7
| | | | | | | | | | | | | | | | | | | | | People often ask questions about the init process and when things go from flash to relocated base, so clarify the comments a bit. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: just set SP register directly during initMike Frysinger2009-01-28-3/+2
| | | | | | | | | | | | | | | | | | | | | No need to set the SP register indirectly to the configured value when it can be set directly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: add portmuxing for UARTs on the BF51xMike Frysinger2009-01-28-1/+10
| | | | | | | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: respect CONFIG_CLKIN_HALFMike Frysinger2009-01-28-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | As pointed out by Ivan Koryakovskiy, the initialization code was not actually respecting the CONFIG_CLKIN_HALF option when configuring the PLL_CTL register. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: use common memcpy routine during initMike Frysinger2009-01-28-21/+11
| | | | | | | | | | | | | | | | | | | | | Rather than using a local custom memcpy function, just call the existing optimized Blackfin version. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: overhaul i2c driverMike Frysinger2009-01-28-429/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The current Blackfin i2c driver does not work properly with certain devices due to it breaking up transfers incorrectly. This is a rewrite of the driver and relocates it to the newer place in the source tree. Also remove duplicated I2C speed defines in Blackfin board configs and disable I2C slave address usage since it isn't implemented. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: fix dcache handling when doing dma memcpy'sMike Frysinger2009-01-28-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | Our dcache invalidate function doesn't just invalidate, it also flushes. So rename the function accordingly and fix the dma_memcpy() function so it doesn't inadvertently corrupt the data destination. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | | Blackfin: minimize time cache is turned off when replacing cplb entriesMike Frysinger2009-01-28-22/+9
|/ / | | | | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* | Command usage cleanupPeter Tyser2009-01-28-4/+4
| | | | | | | | | | | | | | | | Remove command name from all command "usage" fields and update common/command.c to display "name - usage" instead of just "usage". Also remove newlines from command usage fields. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Standardize command usage messages with cmd_usage()Peter Tyser2009-01-28-8/+8
| | | | | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2009-01-27-0/+28
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| * | MIPS: Add flush_dcache_range() and invalidate_dcache_range()Stefan Roese2009-01-27-0/+28
| |/ | | | | | | | | | | | | | | | | | | This patch adds flush_/invalidate_dcache_range() to the MIPS architecture. Those functions are needed for the upcoming dcache support for the USB EHCI driver. I chose this API because those cache handling functions are already present in the PPC architecture. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* | ppc4xx: Improve DDR autodetectDirk Eibach2009-01-26-5/+50
|/ | | | | | | | | Added support for a second memory bank to DDR autodetection for 440 platforms. Made hardcoded values configurable. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-01-24-36/+78
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| * Add secondary CPUs processor frequency for e500 coreHaiying Wang2009-01-23-8/+24
| | | | | | | | | | | | | | | | | | This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| * fsl-ddr: use the 1T timing as default configurationDave Liu2009-01-23-1/+1
| | | | | | | | | | | | | | | | | | For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+13
| | | | | | | | | | | | | | | | - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
| | | | | | | | | | | | | | | | According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-4/+12
| | | | | | | | | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-4/+12
| | | | | | | | | | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-01-24-43/+376
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| * \ Merge branch 'next'Kim Phillips2009-01-23-43/+376
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| | * 83xx: Use the proper sequence for updating IMMR.Scott Wood2009-01-21-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
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