summaryrefslogtreecommitdiff
path: root/cpu
Commit message (Collapse)AuthorAgeLines
* fsl: improve the PIXIS code and fix a few bugsTimur Tabi2010-04-07-1/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Refactor and document the Freescale PIXIS code, used on most 85xx and 86xx boards. This makes the code easier to read and more flexible. Delete pixis.h, because none of the exported functions were actually being used by any other file. Make all of the functions in pixis.c 'static'. Remove "#include pixis.h" from every file that has it. Remove some unnecessary #includes. Make 'pixis_base' into a macro, so that we don't need to define it in every function. Add "while(1);" loops at the end of functions that reset the board, so that execution doesn't continue while the reset is in progress. Replace in_8/out_8 calls with clrbits_8, setbits_8, or clrsetbits_8, where appropriate. Replace ulong/uint with their spelled-out equivalents. Remove unnecessary typecasts, changing the types of some variables if necessary. Add CONFIG_SYS_PIXIS_VCFGEN0_ENABLE and CONFIG_SYS_PIXIS_VBOOT_ENABLE to make it easier for specific boards to support variations in the PIXIS registers sets. No current boards appears to need this feature. Fix the definition of CONFIG_SYS_PIXIS_VBOOT_MASK for the MPC8610 HPCD. Apparently, "pixis_reset altbank" has never worked on this board. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greaterSandeep Gopalpet2010-04-07-0/+14
| | | | | | | The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
* 85xx: Added various P1012/P1013/P1021/P1022 definesKumar Gala2010-04-07-4/+40
| | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add defines for BUCSR bits to make code more readableKumar Gala2010-04-07-5/+7
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: change the default burst mode for DDR3Dave Liu2010-04-07-4/+10
| | | | | | | For 64B cacheline SoC, set the fixed 8-beat burst len, for 32B cacheline SoC, set the On-The-Fly as default. Signed-off-by: Dave Liu <daveliu@freescale.com>
* fsl-ddr: Fix the turnaround timing for TIMING_CFG_4Dave Liu2010-04-07-9/+17
| | | | | | | | | | Read-to-read/Write-to-write turnaround for same chip select of DDR3 memory, BL/2+2 cycles is enough for them at BC4 and OTF case, BL/2 cycles is enough for fixed BL8. Cutting down the turnaround from BL/2+4 to BL/2+2 or BL/2 will improve the memory performance. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Merge branch 'next'Wolfgang Denk2010-04-01-1112/+200
|\
| * Merge remote branch 'origin/master' into nextWolfgang Denk2010-03-29-5/+60
| |\
| * | ColdFire: Cache update for all platformsTsiChung Liew2010-03-24-597/+32
| | | | | | | | | | | | | | | | | | | | | The CF will call cache functions in lib_m68/cache.c and the cache settings are defined in platform configuration file. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | ColdFire: Misc update for M53017TsiChung Liew2010-03-24-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reside Ethernet buffer descriptors in SRAM instead of DRAM. Add CONFIG_SYS_TX_ETH_BUFFER in platform configuration file. Update DRAM control and SRAM control register setting. Update cache setting where size does not write to proper region. Signed-off-by: TsiChung Liew <tsicliew@gmail.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| * | ColdFire: Add CPU compile flag for mcf5301x and mcf532xTsiChung Liew2010-03-24-0/+12
| | | | | | | | | | | | | | | | | | Add CPU compile flag -mcpu=53015 in cpu/config.mk Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | ColdFire: Relocate vector table - mcf5445xTsiChung Liew2010-03-24-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Newer ColdFire processors family boot from address 0 instead of 0xFFnn_nnnn. When the boot flash base chip select is set at new location instead of 0, an un-predictable error will occur if there is an vector being trigger and refer it to an invalid address or the vector table handler is not existed at address 0. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | ColdFire: Update processors' serial port configurationTsiChung Liew2010-03-24-51/+105
| | | | | | | | | | | | | | | | | | | | | Provide parameter passing to uart_port_config(). Update port configuration - un-mask it before enable the bits. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | ColdFire: Correct bit definitionTsiChung Liew2010-03-24-22/+22
| | | | | | | | | | | | | | | | | | | | | Use correct definition for _MASK and _UNMASK. It was combined in the previous used and causes confusion. Signed-off-by: TsiChung Liew <tsicliew@gmail.com>
| * | Adding EP2500 MCF5282 board [PATCH]Michael Durrant2010-03-24-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Mercury-EP2500.patch - added Mercury's EP2500 board uses the mcf5282 processor CREDITS.patch Signed-off-by: David Wu <davidwu@arcturusnetworks.com> Signed-off-by: Michael Durrant <mdurrant@arcturusnetworks.com>
| * | Merge remote branch 'origin/master' into nextWolfgang Denk2010-03-22-18/+13
| |\ \
| * \ \ Merge remote branch 'origin/master' into nextWolfgang Denk2010-03-21-2/+2
| |\ \ \
| * | | | nios2: Added support to YANU UARTRenato Andreola2010-03-21-1/+167
| | | | | | | | | | | | | | | | | | | | Signed-off-by: Scott McNutt <smcnutt@psyent.com>
| * | | | mpc5xxx: Remove all references to MGT5100Detlev Zundel2010-03-21-443/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | We do not support a processor that never reached a real customer. Signed-off-by: Detlev Zundel <dzu@denx.de>
* | | | | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-03-30-14/+102
|\ \ \ \ \
| * | | | | mpc86xx: set the DDR BATs after calculating true DDR sizeTimur Tabi2010-03-30-1/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | After determining how much DDR is actually in the system, set DBAT0 and IBAT0 accordingly. This ensures that the CPU won't attempt to access (via speculation) addresses outside of actual memory. On 86xx systems, DBAT0 and IBAT0 (the BATs for DDR) are initialized to 2GB and kept that way. If the system has less than 2GB of memory (typical for an MPC8610 HPCD), the CPU may attempt to access this memory during speculation. The zlib code is notorious for generating such memory reads, and indeed on the MPC8610, uncompressing the Linux kernel causes a machine check (without this patch). Currently we are limited to power of two sized DDR since we only use a single bat. If a non-power of two size is used that is less than CONFIG_MAX_MEM_MAPPED u-boot will crash. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | | | 85xx: Fix enabling of L1 cache parity on secondary coresKumar Gala2010-03-30-13/+63
| | |_|_|/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | | | ppc4xx: Fix problem with I2C bus >= 1 initializationStefan Roese2010-03-30-1/+4
|/ / / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem introduced with patch eb5eb2b0 [ppc4xx: Cleanup PPC4xx I2C infrastructure]. We need to assign the I2C base address to the "i2c" pointer inside of the controller loop. Otherwise controller 0 is initialized multiple times instead of initializing each I2C controller sequentially. Tested on Katmai. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Heiko Schocher <hs@denx.de>
* | | | ppc4xx fix unstable 440EPx bootstrap optionsRupjyoti Sarmah2010-03-24-5/+60
| |_|/ |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | 440EPx fixed bootstrap options A, B, D, and E sets PLL FWDVA to a value = 1. This results in the PLLOUTB being greater than the CPU clock frequency resulting unstable 440EPx operation resulting in various software hang conditions. This patch reprograms the FWDVA satisfying the requirement of setting FWDVB to a value greater than 1 while using one of the four deafult bootstrap options. Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com> Acked-by : Victor Gallardo <vgallardo@appliedmicro.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | ep93xx timer: Fix resolution of get_ticks()Matthias Kaehlcke2010-03-22-6/+9
| | | | | | | | | | | | | | | | | | | | | ep93xx timer: Make get_ticks() return a value in CONFIG_SYS_HZ resolution, as announced by get_tbclk() Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
* | | ep93xx timer: Fix possible overflow in usecs_to_ticks()Matthias Kaehlcke2010-03-22-12/+4
| |/ |/| | | | | | | | | | | ep93xx timer: Use 64-bit values in usecs_to_ticks() in order to avoid overflows in intermediate values Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
* | mpc5121: cpu/mpc512x/diu.c: fix warningsAnatolij Gustschin2010-03-21-2/+2
| | | | | | | | | | | | | | | | | | | | | | Fix warnings while compiling with CONFIG_VIDEO enabled: diu.c: In function 'video_hw_init': diu.c:158: warning: 'return' with no value, in function returning non-void diu.c:162: warning: format '%ld' expects type 'long int', but argument 6 has type 'int' diu.c:162: warning: format '%ld' expects type 'long int', but argument 7 has type 'int' Signed-off-by: Anatolij Gustschin <agust@denx.de>
* | mod change 755 => 644 for multiple filesThomas Weber2010-03-21-0/+0
| | | | | | | | | | | | | | | | I executed 'find . -name "*.[chS]" -perm 755 -exec chmod 644 {} \;' Signed-off-by: Thomas Weber <swirl@gmx.li> Add some more: neither Makefile nor config.mk need execute permissions. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | nios2: Added support to YANU UARTRenato Andreola2010-03-16-1/+167
|/ | | | Signed-off-by: Scott McNutt <smcnutt@psyent.com>
* Prepare v2010.03-rc1v2010.03-rc1Wolfgang Denk2010-03-12-14/+13
| | | | | | Coding style cleanup, update CHANGELOG. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Update .gitignore's: add some generated filesWolfgang Denk2010-03-12-0/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* updates the at91 main_clock calculationJens Scharsig2010-03-07-3/+4
| | | | | | | * updates the conditional main_clock calculation (if AT91_MAIN_CLOCK defined) to c structure SoC access * add need register flags Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* MX51: removed warnings for the mx51evkStefano Babic2010-03-07-3/+10
| | | | | | | | | | | The patch removes warnings at compile time and provides some cleanup code: - Removed comment on NAND (not yet supported) from lowlevel_init.S - Removed NFMS bit definition from imx-regs.h The bit is only related to MX.25/35 and can lead to confusion - Moved is_soc_rev() to soc specific code (removed from mx51evk.c) Signed-off-by: Stefano Babic <sbabic@denx.de>
* fec_mxc: cleanup and factor out MX27 dependenciesJohn Rigby2010-03-07-0/+5
| | | | | | | | | | | | | general cleanup move clock init to cpu_eth_init in cpu/arm926ejs/mx27/generic.c make MX27 specific phy init conditional on CONFIG_MX27 replace call to imx_get_ahbclk with one to imx_get_fecclk and define imx_get_fecclk in include/asm-arm/arch-mx27/clock.h Signed-off-by: John Rigby <jcrigby@gmail.com> CC: Ben Warren <biggerbadderben@gmail.com> CC: Fred Fan <fanyefeng@gmail.com> CC: Tom <Tom.Rix@windriver.com>
* Add support for Freescale MX25 SOCJohn Rigby2010-03-07-0/+552
| | | | | | | | | ARM926EJS core with MX31 peripherals. Signed-off-by: John Rigby <jcrigby@gmail.com> Earlier Version Signed-off-by: Wolfgang Denk <wd@denx.de> CC: Fred Fan <fanyefeng@gmail.com> CC: Tom <Tom.Rix@windriver.com>
* fsl_esdhc: add support for mx51 processorStefano Babic2010-03-07-1/+39
| | | | | | | | | The esdhc controller in the mx51 processor is quite the same as the one in some powerpc processors (MPC83xx, MPC85xx). This patches adapts the driver to support the arm mx51. Signed-off-by: Stefano Babic <sbabic@denx.de>
* MX51: Add initial support for the Freescale MX51Stefano Babic2010-03-07-0/+1084
| | | | | | | | The patch add initial support for the Freescale i.MX51 processor (family arm cortex_a8). Signed-off-by: Stefano Babic <sbabic@denx.de> Signed-off-by: Fred Fan <fanyefeng@gmail.com>
* Add bootcount to AT91Anders Darander2010-03-07-0/+34
| | | | | | | Use AT91_GPBR 3 as a bootcount register. The bootmagic and the bootcount shares AT91_GPBR 3. Signed-off-by: Anders Darander <ad@datarespons.se>
* ep93xx: Refactoring of timer codeMatthias Kaehlcke2010-03-07-44/+26
| | | | | | | | | | | | | ep93xx: Refactoring of the timer code, including the following changes * use a free running timer instead of a periodical one * use unsigned long long for total number of ticks * hold the timer state in a structure instead of separate variables * increment the timer counter instead of decrementing it * remove unused function udelay_masked() * remove unused function set_timer() Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
* ep93xx: Fix calculation of sys ticks in clk_to_systicks()Matthias Kaehlcke2010-03-07-2/+4
| | | | | | | ep93xx: Use unsigned long long for calculation of sys ticks in clk_to_systicks() for proper handling of large intermediate values Signed-off-by: Matthias Kaehlcke <matthias@kaehlcke.net>
* OMAP3: workaround for ARM Cortex-A8 erratum 725233Siarhei Siamashka2010-03-07-0/+6
| | | | | | | | | | | | | | | | | | | | | | 725233: PLD instructions executed with PLD data forwarding enabled can result in a processor deadlock This deadlock can happen when NEON load instructions are used together with cache preload instructions (PLD). The problematic conditions can be triggered in-the-wild by NEON optimized functions from pixman library (http://cgit.freedesktop.org/pixman), which perform dynamic adjustment of prefetch distance. The workaround disables PLD data forwarding by setting PLD_FWD bit in L2 Cache Auxiliary Control Register as recommended in ARM Cortex-A8 errata list. The deadlock can only happen on r1pX revisions of Cortex-A8 (used in OMAP34xx/OMAP35xx). Performance impact of the workaround is practically non-existant. Signed-off-by: Siarhei Siamashka <siarhei.siamashka@gmail.com> Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* ARM change name of defines for AT91 arm926ejsAchim Ehrlich2010-03-07-5/+5
| | | | | | | | | | Configuration defines should be preceeded with CONFIG_SYS_. Renamed some at91 specific defines to conform to this naming convention: AT91_CPU_NAME to CONFIG_SYS_AT91_CPU_NAME AT91_MAIN_CLOCK to CONFIG_SYS_AT91_MAIN_CLOCK Signed-off-by: Achim Ehrlich <aehrlich@taskit.de>
* Merge branch 'next' of git://git.denx.de/u-boot-coldfireWolfgang Denk2010-03-04-1/+47
|\
| * allow MCF532x to use CONFIG_MONITOR_IS_IN_RAMWolfgang Wegner2010-03-04-0/+7
| | | | | | | | | | | | | | | | | | | | | | CONFIG_MONITOR_IS_IN_RAM is broken for MCF532x. This patch fixes this by conditionally - removing the vector table at the beginning of code - not overwriting the vector base register - removing the code to re-set the PLL, which effectively disables SDRAM access Signed-off-by: Wolfgang Wegner <w.wegner@astro-kom.de>
| * MCF5271-only: Added a weak board_reset function to allow custom resetRichard Retanubun2010-03-04-0/+39
| | | | | | | | | | | | | | | | | | | | | | This patch adds a board_reset function to allow boards to specify their own custom reset sequence (e.g. resetting by timing out watchdog). Tested only on MCF5271, can be expanded if needed. Based on Mike Frysinger's suggestion on: http://article.gmane.org/gmane.comp.boot-loaders.u-boot/70304 Signed-off-by: Richard Retanubun <RichardRetanubun at RuggedCom.com>
| * MCF532x: make icache_enable use CONFIG_SYS_SDRAM_SIZEWolfgang Wegner2010-03-04-1/+1
| | | | | | | | | | | | | | | | in cpu/mcf532x/start.S, the function icache_enable enables the cache for a fixed 32MB region starting at the SDRAM start address; this patch changes the function to cover the region defined by CONFIG_SYS_SDRAM_SIZE Signed-off-by: Wolfgang Wegner <w.wegner at astro-kom.de>
* | Bug: do_reset issued via netconsole does not reset mpc83xx cpu.Michael Zaidman2010-02-18-5/+3
|/ | | | | | | | | | | | The do_reset routine in the cpu/mpc83xx/cpu.c file does not reset the mpc83xx cpu when issued via netconsole. Moving the console output "resetting the board." to the beginning of the routine before disabling interrupts solved the problem. Signed-off-by: Michael Zaidman <michael.zaidman@gmail.com> Acked-by: Detlev Zundel <dzu@denx.de> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* prepare joining at91rm9200 into at91Jens Scharsig2010-02-12-0/+437
| | | | | | | | | | | | * prepare joining at91 and at91rm9200 * add modified copy of soc files to cpu/arm920t/at91 to make possible to compile at91rm9200 boards in at91 tree instead of at91rm9200 * add header files with c structure defs for AT91 MC, ST and TC * the new cpu files are using at91 c structure soc access * please read README.soc-at91 for details Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* convert common files to new SoC accessJens Scharsig2010-02-12-121/+208
| | | | | | | | * add's a warning to all files, which need update to new SoC access * convert common files in cpu/../at91 and a lot of drivers to use c stucture SoC access Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
* convert all at91 files to use at91_gpio driver syntaxJens Scharsig2010-02-12-249/+249
| | | | | | | | | * convert all files cpu/../at91 to use at91_gpio driver syntax * change AT91_PINP([A-F])(\d+) to AT91_PIO_PORT\1, \2 this makes all 160 AT91_PINPxxx defines obsolete * AT91_PINPxxx defines and gpio.h can be remove, if all boards converted to new SoC access Signed-off-by: Jens Scharsig <js_at_ng@scharsoft.de>
generated by cgit v1.1 at 2024-11-10 19:57:37 +0000