summaryrefslogtreecommitdiff
path: root/cpu
Commit message (Collapse)AuthorAgeLines
* Blackfin: fix up UART status bit handlingMike Frysinger2008-10-23-12/+60
| | | | | | | | Some Blackfin UARTs are read-to-clear while others are write-to-clear. This can cause problems when we poll the LSR and then later try and handle any errors detected. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: small cpu init optimization while setting interrupt maskMike Frysinger2008-10-23-5/+2
| | | | | | | Use the sti instruction to set the initial interrupt mask rather than banging on the core IMASK MMR to save both space and time. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: set initial stack correctly according to Blackfin ABIMike Frysinger2008-10-23-3/+3
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: make baud calculation more accurateMike Frysinger2008-10-23-4/+4
| | | | | | | | We should use the algorithm in the Linux kernel so that the UART divisor calculation is more accurate. It also fixes problems on some picky UARTs that have sampling anomalies. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: decode hwerrcause/excause when crashingMike Frysinger2008-10-23-2/+40
| | | | | | Having to decode hwerrcause/excause values is a pain, so automate it. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: fix register dump messagesMike Frysinger2008-10-23-1/+5
| | | | | | Make sure we report RETI/IPEND correctly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: don't bother displaying reboot msg when crashingMike Frysinger2008-10-23-5/+1
| | | | | | | The hang function already tells you to reboot, so no point in showing it twice. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: enable support for nested interruptsMike Frysinger2008-10-23-4/+10
| | | | | | | During cpu init, make sure we initialize the CEC properly so that interrupts can fire and be handled while U-Boot is running. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: drop unused cache flush codeMike Frysinger2008-10-23-231/+1
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: unify cache handling codeMike Frysinger2008-10-23-35/+0
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: only enable hardware error irq by defaultMike Frysinger2008-10-23-3/+2
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* mpc83xx: Removed #ifdef CONFIG_MPC834X dependency on upmconfig functionRichard Retanubun2008-10-21-5/+0
| | | | | | | | This is done to allow other 83XX based platforms which also have UPM (e.g. 8360) to configure and use their UPM in u-boot. Signed-off-by: Richard Retanubun <RichardRetanubun@RuggedCom.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* mpc83xx: serdes: add forgotten shifts for rfcksAnton Vorontsov2008-10-21-1/+1
| | | | | | | | | | The rfcks should be shifted by 28 bits left. We didn't notice the bug because we were using only 100MHz clocks (for which rfcks == 0). Though, for SGMII we'll need 125MHz clocks. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-36/+99
|\
| * ppc4xx: Correctly setup ranges property in ebc nodeStefan Roese2008-10-21-17/+28
| | | | | | | | | | | | | | | | Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add routine to retrieve CPU numberAdam Graham2008-10-21-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add static support for 44x IBM SDRAM ControllerAdam Graham2008-10-21-18/+53
| | | | | | | | | | | | | | | | | | | | This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-12/+12
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Use strmhz() to format clock frequenciesWolfgang Denk2008-10-21-73/+99
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge git://git.denx.de/u-boot into x1Markus Klotzbuecher2008-10-21-3657/+3816
|\ \ | |/ | | | | | | | | Conflicts: drivers/usb/usb_ohci.c
| * Merge 'next' branchWolfgang Denk2008-10-18-3476/+3673
| |\ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * 85xx if NUM_CPUS>1, print cpu numberEd Swarthout2008-10-18-0/+5
| | | | | | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| | * Have u-boot pass stashing parameters into device treeAndy Fleming2008-10-18-0/+11
| | | | | | | | | | | | | | | | | | | | | | | | | | | Some cores don't support ethernet stashing at all, and some instances have errata. Adds 3 properties to gianfar nodes which support stashing. For now, just add this support to 85xx SoCs. Signed-off-by: Andy Fleming <afleming@freescale.com>
| | * Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
| | | | | | | | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Check DDR interleaving modeHaiying Wang2008-10-18-5/+112
| | | | | | | | | | | | | | | | | | | | | | | | | | | * Check DDR interleaving mode from environment by reading memctl_intlv_ctl and ba_intlv_ctl. * Print DDR interleaving mode information * Add doc/README.fsl-ddr to describe the interleaving setting Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-87/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Because some dimm parameters like n_ranks needs to be used with the board frequency to choose the board parameters like clk_adjust etc. in the board_specific_paramesters table of the board ddr file, we need to pass the dimm parameters to the board file. * move ddr dimm parameters header file from /cpu to /include directory. * add ddr dimm parameters to populate board specific options. * Fix fsl_ddr_board_options() for all the 8xxx boards which call this function. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-12/+54
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix some bugs: 1. Correctly set intlv_ctl in cs_config. 2. Correctly set sa, ea in cs_bnds when bank interleaving mode is enabled. 3. Set base_address and total memory for each ddr controller in memory controller interleaving mode. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| | * 85xx: Export invalidate_{i,d}cache and add flush_dcacheKumar Gala2008-10-18-0/+49
| | | | | | | | | | | | | | | | | | | | | | | | Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-3365/+3365
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| | * 74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx versionKumar Gala2008-10-18-10/+10
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * I2C: adding new "i2c bus" Command to the I2C Subsystem.Heiko Schocher2008-10-18-1/+14
| | | | | | | | | | | | | | | | | | | | | With this Command it is possible to add new I2C Busses, which are behind 1 .. n I2C Muxes. Details see README. Signed-off-by: Heiko Schocher <hs@denx.de>
| | * i2c: add CONFIG_I2C_MULTI_BUS for soft_i2c and mpc8260 i2c driver.Heiko Schocher2008-10-18-0/+36
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| | * Adds two more ethernet interface to 83xxrichardretanubun2008-10-18-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Added as a convenience for other platforms that uses MPC8360 (has 8 UCC). Six eth interface is chosen because the platform I am using combines UCC1&2 and UCC3&4 as 1000 Eth and the other four UCCs as 10/100 Eth. Signed-off-by: Richard Retanubun <RichardRetanubun@RugggedCom.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | 83xx NAND boot: wait for LTESR[CC]Lepcha Suchit2008-10-17-0/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | At least some revisions of the 8313, and possibly other chips, do not wait for all pages of the initial 4K NAND region to be loaded before beginning execution; thus, we wait for it before branching out of the first NAND page. This fixes warm reset problems when booting from NAND on 8313erdb. Signed-off-by: Scott Wood <scottwood@freescale.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
| * | ppc4xx: PPC44x MQ initializationYuri Tikhonov2008-10-17-4/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Comment from Stefan: This patch doesn't change the resulting value of the MQ registers. It explicitly sets/clears all bits to the desired state which better documents the resulting register value instead of relying on pre-set default values. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | Revert "85xx: Using proper I2C source clock divider for MPC8544"Kumar Gala2008-10-17-2/+2
| |/ | | | | | | | | | | | | | | | | | | This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159. The fix introduced by this patch is not correct. The problem is that the documentation is not correct for the MPC8544 with regards to which bit in PORDEVSR2 is for the SEC_CFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * mpc83xx: wait till UPM completes the write to arraySelvamuthukumar2008-10-14-3/+4
| | | | | | | | | | | | | | | | | | | | | | Reference manual states that MxMR[MAD] increment is the indication of write to UPM array is complete. Honour that. Also, make the dummy write explicit. also fix the comment. Signed-off-by: Selvamuthukumar <selva.muthukumar@e-coninfotech.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheNick Spence2008-10-13-4/+4
| | | | | | | | | | | | | | | | | | | | This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com>
| * 86xx: remove redudant code with lib_ppc/interrupts.cKumar Gala2008-10-13-124/+7
| | | | | | | | | | | | | | | | | | | | For some reason we duplicated the majority of code in lib_ppc/interrupts.c Not know how that happened, but there is no good reason for it. Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-10-13-37/+57
| |\
| | * Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2008-10-12-29/+50
| | |\
| | | * i.MX31: switch to CFG_HZ=1000Guennadi Liakhovetski2008-10-08-29/+50
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Switch to the standard CFG_HZ=1000 value, while at it, minor white-space cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads, provides 2% or 0.4% precision depending on the CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s boot-delay. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
| | * | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-10-12-7/+6
| | |\ \
| | | * | 85xx: Using proper I2C source clock divider for MPC8544Wolfgang Grandegger2008-10-08-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
| | | * | Fix the incorrect DDR clk freq reporting on 8536DSJason Jin2008-10-07-2/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
| | | * | 85xx: Remove setting of *cache-line-size in device treesKumar Gala2008-10-07-3/+0
| | | |/ | | | | | | | | | | | | | | | | | | | | | | | | ePAPR says if the *cache-block-size is the same as *cache-line-size than we don't need the *cache-line-size property. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| | * | mpc83xx: spd_sdram: fix ddr sdram base address assignment bugAnton Vorontsov2008-09-24-1/+1
| | |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The spd_dram code shifts the base address, then masks 20 bits, but forgets to shift the base address back. Fix this by just masking the base address correctly. Found this bug while trying to relocate a DDR memory at the base != 0. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR changeAdam Graham2008-10-08-0/+21
| |/ | | | | | | | | | | | | | | | | | | | | | | After changing SDRAM_CLKTR phase value rerun the memory preload initialization sequence (INITPLR) to reset and relock the memory DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects the phase relationship of the internal, to the PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * Fix DPRAM memory leak when CFG_ALLOC_DPRAM is defined, whichWolfgang Denk2008-09-22-4/+6
| | | | | | | | | | | | | | | | eventually leads to a machine check. This change assures that DPRAM is allocated only once in that case. Signed-off-by: Gary Jennejohn <garyj@denx.de> Signed-off-by: Wolfgang Denk <wd@denx.de>
| * sh: Add support watchdog for SH4A coreNobuhiro Iwamatsu2008-09-19-16/+37
| | | | | | | | | | | | | | Add support watchdog for SH4A core (SH7763, SH7780 and SH7785). And fix some compile warning. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
generated by cgit v1.1 at 2024-11-16 20:57:14 +0000