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* Merge branch 'master' of git://git.denx.de/u-boot-armWolfgang Denk2008-09-01-79/+1410
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| * USB: Add support for OHCI controller on S3C6400Guennadi Liakhovetski2008-08-31-0/+46
| | | | | | | | | | | | | | | | Notice: USB on S3C6400 currently works _only_ with switched off MMU. One could try to enable the MMU, but map addresses 1-to-1, and disable data cache, then it should work too and we could still profit from instruction cache. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
| * ARM: Add arm1176 core with S3C6400 SoCGuennadi Liakhovetski2008-08-31-0/+1285
| | | | | | | | | | | | Based on the original S3C64XX port by Samsung for U-Boot 1.1.6. Signed-off-by: Guennadi Liakhovetski <lg@denx.de>
| * ARM DaVinci: Changing function names for EMAC driverSandeep Paulraj2008-08-31-79/+79
| | | | | | | | | | | | | | | | | | | | DM644x is just one of a series of DaVinci chips that use the EMAC driver. By replacing all the function names that start with dm644x_* to davinci_* we make these function more portable. I have tested this change on my EVM. DM6467 is another DaVinci SOC which uses the EMAC driver and i will be sending patches that add DaVinci DM6467 support to the list soon. Signed-off-by: Sandeep Paulraj <s-paulraj@ti.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-09-01-20/+71
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| * | ppc4xx/NAND: Add select_chip function to 4xx NDFC driverStefan Roese2008-08-30-0/+8
| | | | | | | | | | | | | | | | | | | | | This function is needed for the new NAND infrastructure. We only need a dummy implementation though for the NDFC. Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: NAND configurationWolfgang Ocker2008-08-29-1/+5
| | | | | | | | | | | | | | | | | | | | | Made NAND bank configuration setting a config variable. Signed-off-by: Wolfgang Ocker <weo@reccoware.de> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: fix UIC external_interrupt hang on UIC0Victor Gallardo2008-08-29-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a UIC external_interrupt hang if critical or non-critical interrupt is set at the same time as a normal interrupt is set on UIC0. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Optimizations/Cleanups for IBM DDR2 Memory ControllerProdyut Hazarika2008-08-29-17/+56
| |/ | | | | | | | | | | | | | | | | Removed Magic numbers from Initialization preload registers Tested with Kilauea, Glacier, Canyonlands and Katmai boards About 5-7% improvement seen for LMBench memtests Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of git://git.denx.de/u-boot-shWolfgang Denk2008-09-01-0/+546
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| * | sh: Add support SH2/SH2A which is CPU of Renesas TechnologyNobuhiro Iwamatsu2008-08-31-0/+546
| |/ | | | | | | | | | | | | Add support SH2/SH2A basic function. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro@renesas.com> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2008-08-31-2469/+2
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| * | Move MPC512x_FEC driver to drivers/netBen Warren2008-08-29-1022/+1
| | | | | | | | | | | | Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
| * | Move MPC5xxx_FEC driver to drivers/netBen Warren2008-08-29-1447/+1
| |/ | | | | | | Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | ColdFire: I2C fix for multiple platformsTsiChung Liew2008-08-28-3/+43
|/ | | | Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2008-08-28-2/+4
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| * Merge branch 'master' of git://git.denx.de/u-boot-mpc5xxxWolfgang Denk2008-08-28-2/+4
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| | * mpc52xx: added support for the MPC5200 based MUC.MC52 board from MAN.Heiko Schocher2008-08-27-2/+4
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.Kumar Gala2008-08-28-1/+0
|/ / | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-08-28-1260/+589
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| * | mpc85xx: remove redudant code with lib_ppc/interrupts.cKumar Gala2008-08-27-97/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For some reason we duplicated the majority of code in lib_ppc/interrupts.c not show how that happened, but there is no good reason for it. Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | mpc85xx: Add support for the MPC8536Kumar Gala2008-08-27-1/+199
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-2/+2
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | FSL DDR: Remove old SPD support from cpu/mpc85xxKumar Gala2008-08-27-1166/+0
| | | | | | | | | | | | | | | | | | | | | All 85xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | FSL DDR: Add 85xx specific register settingKumar Gala2008-08-27-0/+318
| | | | | | | | | | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | FSL DDR: Add e500 TLB helper for DDR codeKumar Gala2008-08-27-0/+64
| |/ | | | | | | | | | | | | Provide a helper function that board code can call to map TLBs when setting up DDR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | Moved initialization of GRETH Ethernet driver to CPU directoryBen Warren2008-08-26-0/+17
| | | | | | | | | | | | | | Added a cpu_eth_init() function to leon2/leon3 CPU directories and removed code from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Moved initialization of MCFFEC Ethernet driver to CPU directoryBen Warren2008-08-26-2/+71
| | | | | | | | | | | | | | Added a cpu_eth_init() function to coldfire CPU directories and removed code from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Moved initialization of FSL_MCDMAFEC Ethernet driver to CPU directoryBen Warren2008-08-26-0/+9
|/ | | | | | | Added a cpu_eth_init() function to cpu/mcf547x_8x directory and removed code from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* FSL DDR: Remove old SPD support from cpu/mpc86xxKumar Gala2008-08-27-1352/+0
| | | | | | | All 86xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add 86xx specific register settingKumar Gala2008-08-27-0/+92
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add DDR2 DIMM paramter supportKumar Gala2008-08-27-0/+339
| | | | | | | | Compute DIMM parameters based upon the SPD information. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add DDR1 DIMM paramter supportKumar Gala2008-08-27-0/+343
| | | | | | | | Compute DIMM parameters based upon the SPD information in spd. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-2/+2432
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc83xx: add PCISLAVE support to 83XX_GENERIC_PCI setup codeIra W. Snyder2008-08-25-0/+26
| | | | | | | | | This adds a helper function to unlock the PCI configuration bit, so that any extra PCI setup (such as outbound windows, etc.) can be done after using the 83XX_GENERIC_PCI code to set up the PCI bus. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* Minor coding style cleanup, updte CHANGELOGWolfgang Denk2008-08-25-7/+7
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* MX31: fix bit masks in function mx31_decode_pll()Jens Gehrlein2008-08-25-2/+2
| | | | | | Bits MPCTL[MFN] and MPCTL[MFD] were not fully covered. Signed-off-by: Jens Gehrlein <sew_s@tqs.de>
* Correct ARM Versatile Timer InitializationGururaja Hebbar K R2008-08-25-4/+35
| | | | | | | | | | | | | | | - According to ARM Dual-Timer Module (SP804) TRM (ARM DDI0271), -- Timer Value Register @ TIMER Base + 4 is Read-only. -- Prescale Value (Bits 3-2 of TIMER Control register) can only be one of 00,01,10. 11 is undefined. -- CFG_HZ for Versatile board is set to #define CFG_HZ (1000000 / 256) So Prescale bits is set to indicate - 8 Stages of Prescale, Clock divided by 256 - The Timer Control Register has one Undefined/Shouldn't Use Bit So we should do read/modify/write Operation Signed-off-by: Gururaja Hebbar <gururajakr@sanyo.co.in>
* ARM DaVinci: Removed redundant NAND initialization code.Hugo Villeneuve2008-08-25-2/+1
| | | | | | ARM DaVinci: Removed redundant NAND initialization code. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
* ARM DaVinci: Fix compilation error with new MTD code.Hugo Villeneuve2008-08-25-2/+0
| | | | | | ARM DaVinci: Fix compilation error with new MTD code. Signed-off-by: Hugo Villeneuve <hugo.villeneuve@lyrtech.com>
* ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fixTirumala R Marri2008-08-22-5/+5
| | | | | | | | | | | During recent PCI-E tests it has been found that current driverl level and de-emphasis values are not set correctly. After sweeping throgh all de-ephasis values, it was found that 0x130 is a right value. Where 0x13 is driver level and 0 is de-emphasis. Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patchStefan Roese2008-08-21-24/+13
| | | | | | | | | | | | | This patch fixes some minor issues introduced with the patch: ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika: - Rework memory-queue and PLB arbiter optimization code, that the local variable is not needed anymore. This removes one #ifdef. - Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead of XXX+ 0x01). This was not introduced by Prodyut, just a copy-paste problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,Prodyut Hazarika2008-08-21-5/+38
| | | | | | | | | | | | | | | PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* fdt: rework fdt_fixup_ethernet() to use env instead of bd_tKumar Gala2008-08-21-8/+8
| | | | | | | | | | Move to using the environment variables 'ethaddr', 'eth1addr', etc.. instead of bd->bi_enetaddr, bi_enet1addr, etc. This makes the code a bit more flexible to the number of ethernet interfaces. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Adding bootlimit/bootcount feature for MPC5XXX on TQM5200 BoardsAxel Beierlein2008-08-21-0/+20
| | | | | | Tested with TQM5200S on STK52XX.200 Board Signed-off-by: Axel Beierlein <belatronix@web.de>
* Merge branch 'next' of git://git.denx.de/u-boot-avr32Haavard Skinnemoen2008-08-20-1/+4
|\ | | | | | | | | | | Conflicts: MAINTAINERS
| * Merge branch 'favr-32' of git://git.denx.de/u-boot-avr32Haavard Skinnemoen2008-08-06-21/+29
| |\ | | | | | | | | | | | | | | | | | | | | | Conflicts: MAINTAINERS MAKEALL Makefile
| * | Add support for the hammerhead (AVR32) boardJulien May2008-07-30-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The Hammerhead platform is built around a AVR32 32-bit microcontroller from Atmel. It offers versatile peripherals, such as ethernet, usb device, usb host etc. The board also incooperates a power supply and is a Power over Ethernet (PoE) Powered Device (PD). Additonally, a Cyclone III FPGA from Altera is integrated on the board. The FPGA is mapped into the 32-bit AVR memory bus. The FPGA offers two DDR2 SDRAM interfaces, which will cover even the most exceptional need of memory bandwidth. Together with the onboard video decoder the board is ready for video processing. For more information see: http:///www.miromico.com/hammerhead Signed-off-by: Julien May <mailinglist@miromico.ch> [haavard.skinnemoen@atmel.com: various small fixes and adaptions] Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen@atmel.com>
* | | Clean up usage of icache_disable/dcache_disableKumar Gala2008-08-19-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | There is no point in disabling the icache on 7xx/74xx/86xx parts and not also flushing the icache. All callers of invalidate_l1_instruction_cache() call icache_disable() right after. Make it so icache_disable() calls invalidate_l1_instruction_cache() for us. Also, dcache_disable() already calls dcache_flush() so there is no point in the explicit calls of dcache_flush(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | | ColdFire: Multiple fixes for M5282EVBTsiChung Liew2008-08-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | Incorrect CFG_HZ value, change 1000000 to 1000. Rename #waring to #warning. RAMBAR1 uses twice in start.S, rename the later to FLASHBAR. Insert nop for DRAM setup. And, env_offset in linker file. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew@freescale.com>
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