| Commit message (Collapse) | Author | Age | Lines |
|\ |
|
| |
| |
| |
| |
| |
| | |
clear the Display after reset.
Signed-off-by: Heiko Schocher <hs@denx.de>
|
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| |
| | |
Now 405EZ ports also show upon bootup from which boot device
they are configured to boot:
U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05)
CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz)
Bootstrap Option E - Boot ROM Location EBC (32 bits)
16 kB I-Cache 16 kB D-Cache
Board: Acadia - AMCC PPC405EZ Evaluation Board
Signed-off-by: Stefan Roese <sr@denx.de>
|
|/
|
|
|
|
|
|
|
|
|
| |
This patch fixes changes the i2c_init(...) function to use the function
get_OPB_freq() rather than calculating the OPB speed by
sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is
specific per processor. The prior method was not and so was calculating
the wrong speed for some PPC4xx processors.
Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com>
Signed-off-by: Stefan Roese <sr@denx.de>
|
|\ |
|
| |\ |
|
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Additional RAM information is now printed upon powerup, like
DDR2 frequency and CAS latency.
Signed-off-by: Stefan Roese <sr@denx.de>
|
| | |
| | |
| | |
| | |
| | |
| | |
| | |
| | | |
Fix a bug in the auto calibration routine. This driver now runs
more reliable with the tested modules. It's also tested with
167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai.
Signed-off-by: Stefan Roese <sr@denx.de>
|
| |\ \ |
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
This patch adds some 4xx GPIO functions. It also moves some of the
common code and defines into a common 4xx GPIO header file.
Signed-off-by: Stefan Roese <sr@denx.de>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
This patch cleans up all the open issue of the preliminary
Acadia support.
Signed-off-by: Stefan Roese <sr@denx.de>
|
| | | | |
|
|\ \ \ \ |
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Reset support
BSP autoconfig support
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
timer support
interrupt controller support
flash support
ethernet support
cache support
board information support
env support
booting image support
adding support for Xilinx ML401
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
timer support
interrupt controller support
flash support
ethernet support
cache support
board information support
env support
booting image support
adding support for Xilinx ML401
|
| | | | | |
|
| |_|_|/
|/| | |
| | | |
| | | | |
Modifications to the existing code to support the new fdt command.
|
|\ \ \ \ |
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Prevent false interrupt from hanging Linux as MSR[EE] is set
to enable interrupts by changing the PIC out of the default
pass through mode into mixed mode.
Signed-off-by: Haiying Wang <haiying.wang@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
Without this patch, I am unable to get to the prompt on rev 2 silicon.
Only set ddrioovcr for rev1.
Signed-off-by: Ed Swarthout<ed.swarthout@freescale.com>
Signed-off-by: Jon Loeliger <jdl@freescale.com>
|
| | | | |
| | | | |
| | | | |
| | | | | |
Signed-off-by: Wolfgang Denk <wd@denx.de>
|
|\ \ \ \ \ |
|
| | | | | | |
|
| |\ \ \ \ \ |
|
| | | | | | | |
|
| | | | | | | |
|
| | | | | | | |
|
| | | | | | | |
|
| | | | | | | |
|
| | | | | | |
| | | | | | |
| | | | | | |
| | | | | | | |
support
|
| | | | | | | |
|
|\ \ \ \ \ \ \
| | |_|_|_|/ /
| |/| | | | | |
|
| |\ \ \ \ \ \
| | |_|/ / / /
| |/| | | | /
| | | |_|_|/
| | |/| | | |
|
| | | |_|/
| | |/| |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | |
| | | | | |
This patch adds support for the new AMCC 405EZ PPC. It is in
preparation for the AMCC Acadia board support.
Please note that this Acadia/405EZ support is still in a beta stage.
Still lot's of cleanup needed but we need a preliminary release now.
Signed-off-by: Stefan Roese <sr@denx.de>
|
| |_|_|/
|/| | |
| | | |
| | | | |
Signed-off-by: Markus Klotzbuecher <mk@denx.de>
|
|/ / /
| | |
| | |
| | |
| | |
| | |
| | | |
for the SIUMCR and BCR Register.
Fix the calculation for the EEprom Size
Signed-off-by: Heiko Schocher <hs@denx.de>
|
|\ \ \
| |_|/
|/| | |
|
| | |
| | |
| | |
| | | |
Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
|
|\ \ \ |
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The config value for:
* CFG_ACR_PIPE_DEP
* CFG_ACR_RPTCNT
* CFG_SPCR_TSEC1EP
* CFG_SPCR_TSEC2EP
* CFG_SCCR_TSEC1CM
* CFG_SCCR_TSEC2CM
Were not being used when setting the appropriate register
Added:
* CFG_SCCR_USBMPHCM
* CFG_SCCR_USBDRCM
* CFG_SCCR_PCICM
* CFG_SCCR_ENCCM
To allow full config of the SCCR.
Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349
that were just bogus.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
8360 and 832x weren't updating their [local-]mac-address
properties. This patch fixes that.
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
Some device trees have a mac-address property, some have local-mac-address,
and some have both. To support all of these device trees, this patch
updates ftp_cpu_setup() to write the MAC address to mac-address if it exists.
This function already updates local-mac-address.
Signed-off-by: Timur Tabi <timur@freescale.com>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The code supply fixed and SPD initialization for MPC83xx DDR2 Controller.
it pass DDR/DDR2 compliance tests.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
MPC8360E rev2.0 have new spridr,and PVR value,
The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM.
Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
MPC8349E rev3.1 have new spridr,and PVR value,
The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM.
Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
don't hang if watchdog configured on 8360, 832x
The watchdog programming model is the same across all 83xx devices;
make the code reflect that.
|
| | | |
| | | |
| | | |
| | | | |
protect memcpy to bad address if a local-mac-address is missing from dt
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all
MPC834X class processors. Change the protections from CONFIG_MPC8349 to
CONFIG_MPC834X so they are more generic.
Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
|
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | |
| | | | |
I've redone the SBC8349 support to match git-current, which
incorporates all the MPC834x updates from Freescale since the 1.1.6
release, including the DDR changes.
I've kept all the SBC8349 files as parallel as possible to the
MPC8349EMDS ones for ease of maintenance and to allow for easy
inspection of what was changed to support this board. Hence the SBC8349
U-Boot has FDT support and everything else that the MPC8349EMDS has.
Fortunately the Freescale updates added support for boards using CS0,
but I had to change spd_sdram.c to allow for board specific settings for
the sdram_clk_cntl (it is/was hard coded to zero, and that remains the
default if the board doesn't specify a value.)
Hopefully this should be mergeable as-is and require no whitespace
cleanups or similar, but if something doesn't measure up then let me
know and I'll fix it.
Thanks,
Paul.
|