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* Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-21-37/+323
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| * [PATCH] Add AMCC PPC405EZ supportStefan Roese2007-03-21-37/+323
| | | | | | | | | | | | | | | | | | | | This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-1/+1
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| * | [PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUSMatthias Fuchs2007-03-08-1/+1
| | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-mpc83xxWolfgang Denk2007-03-08-119/+498
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| * | | mpc83xx: Fix config of Arbiter, System Priority, and Clock ModeKumar Gala2007-03-02-6/+28
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The config value for: * CFG_ACR_PIPE_DEP * CFG_ACR_RPTCNT * CFG_SPCR_TSEC1EP * CFG_SPCR_TSEC2EP * CFG_SCCR_TSEC1CM * CFG_SCCR_TSEC2CM Were not being used when setting the appropriate register Added: * CFG_SCCR_USBMPHCM * CFG_SCCR_USBDRCM * CFG_SCCR_PCICM * CFG_SCCR_ENCCM To allow full config of the SCCR. Also removed random CFG_SCCR settings in MPC8349EMDS, TQM834x, and sbc8349 that were just bogus. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc83xx: update [local-]mac-address properties on UEC based devicesKim Phillips2007-03-02-0/+40
| | | | | | | | | | | | | | | | | | | | | | | | | | | | 8360 and 832x weren't updating their [local-]mac-address properties. This patch fixes that. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * | | mpc83xx: write MAC address to mac-address and local-mac-addressTimur Tabi2007-03-02-0/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, this patch updates ftp_cpu_setup() to write the MAC address to mac-address if it exists. This function already updates local-mac-address. Signed-off-by: Timur Tabi <timur@freescale.com>
| * | | mpc83xx: Add DDR2 controller fixed/SPD Init for MPC83xxXie Xiaobo2007-03-02-61/+323
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The code supply fixed and SPD initialization for MPC83xx DDR2 Controller. it pass DDR/DDR2 compliance tests. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
| * | | mpc83xx: Add the cpu specific code for MPC8360E rev2.0 MDSXie Xiaobo2007-03-02-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8360E rev2.0 have new spridr,and PVR value, The MDS board for MPC8360E rev2.0 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo <X.Xie@freescale.com>
| * | | mpc83xx: Add the cpu and board specific code for MPC8349E rev3.1 MDSXie Xiaobo2007-03-02-3/+14
| | | | | | | | | | | | | | | | | | | | | | | | | | | | MPC8349E rev3.1 have new spridr,and PVR value, The MDS board for MPC8349E rev3.1 has 32M bytes Flash and 256M DDR2 DIMM. Signed-off-by: Xie Xiaobo<X.Xie@freescale.com>
| * | | mpc83xx: don't hang if watchdog configured on 8360, 832xKim Phillips2007-03-02-4/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | don't hang if watchdog configured on 8360, 832x The watchdog programming model is the same across all 83xx devices; make the code reflect that.
| * | | mpc83xx: protect memcpy to bad address if a local-mac-address is missing from dtKim Phillips2007-03-02-0/+2
| | | | | | | | | | | | | | | | protect memcpy to bad address if a local-mac-address is missing from dt
| * | | mpc83xx: Replace CONFIG_MPC8349 and use CONFIG_MPC834X insteadKumar Gala2007-03-02-5/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The code that is ifdef'd with CONFIG_MPC8349 is actually applicable to all MPC834X class processors. Change the protections from CONFIG_MPC8349 to CONFIG_MPC834X so they are more generic. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * | | mpc83xx: U-Boot support for Wind River SBC8349Paul Gortmaker2007-03-02-0/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | I've redone the SBC8349 support to match git-current, which incorporates all the MPC834x updates from Freescale since the 1.1.6 release, including the DDR changes. I've kept all the SBC8349 files as parallel as possible to the MPC8349EMDS ones for ease of maintenance and to allow for easy inspection of what was changed to support this board. Hence the SBC8349 U-Boot has FDT support and everything else that the MPC8349EMDS has. Fortunately the Freescale updates added support for boards using CS0, but I had to change spd_sdram.c to allow for board specific settings for the sdram_clk_cntl (it is/was hard coded to zero, and that remains the default if the board doesn't specify a value.) Hopefully this should be mergeable as-is and require no whitespace cleanups or similar, but if something doesn't measure up then let me know and I'll fix it. Thanks, Paul.
| * | | mpc83xx: Put the version (and magic) after the HRCW.Jerry Van Baren2007-03-02-12/+16
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Put the version (and magic) after the HRCW. This puts it in a fixed location in flash, not at the start of flash but as close as we can get. Signed-off-by: Jerry Van Baren <vanbaren@cideas.com>
| * | | mpc83xx: Add support for the MPC832XEMDS boardDave Liu2007-03-02-16/+44
| | | | | | | | | | | | | | | | | | | | | | | | This patch supports DUART, ETH3/4 and PCI etc. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * | | mpc83xx: streamline the 83xx immr head fileDave Liu2007-03-02-12/+12
| | |/ | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | For better format and style, I streamlined the 83xx head files, including immap_83xx.h and mpc83xx.h. In the old head files, 1) duplicated macro definition appear in the both files; 2) the structure of QE immr is duplicated in the immap_83xx.h and immap_qe.h; 3) The macro definition put inside the each structure. So, I cleaned up the structure of QE immr from immap_83xx.h, deleted the duplicated stuff and moved the macro definition to mpc83xx.h, Just like MPC8260. CHANGELOG *streamline the 83xx immr head file Signed-off-by: Dave Liu <daveliu@freescale.com>
* | | Merge with /home/hs/jupiter/u-bootWolfgang Denk2007-03-08-6/+7
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| * | [PATCH] Added support for the jupiter board.Heiko Schocher2007-02-16-0/+1
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-26/+40
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| * \ \ Merge with /home/stefan/git/u-boot/yucca-ddr2Stefan Roese2007-03-08-26/+40
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| | * | | [PATCH] Update AMCC Luan 440SP eval board supportStefan Roese2007-03-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SPStefan Roese2007-03-08-25/+39
| | | |/ | | |/| | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-07-4/+27
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| * | | [PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM'sStefan Roese2007-03-07-4/+27
| |/ / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem that occurs when 2 DIMM's are used. This problem was first spotted and fixed by Gerald Jackson <gerald.jackson@reaonixsecurity.com> but this patch fixes the problem in a little more clever way. This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. As this feature is new to the "old" 44x SPD DDR driver, it has to be enabled via the CONFIG_PROG_SDRAM_TLB define. Signed-off-by: Stefan Roese <sr@denx.de>
* | | Restructure POST directory to support of other CPUs, boards, etc.Wolfgang Denk2007-03-06-35/+35
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* | Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-03-01-24/+24
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| * | Minor code cleanup.Wolfgang Denk2007-02-27-27/+27
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* | | [PATCH] Update AMCC Katmai 440SPe eval board supportStefan Roese2007-03-01-99/+323
|/ / | | | | | | | | | | | | | | | | | | | | This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-02-20-6/+6
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| * | [PATCH 9_9] Use "void *" not "unsigned long *" for block dev read_write ↵Grant Likely2007-02-20-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | buffer pointers Block device read/write is anonymous data; there is no need to use a typed pointer. void * is fine. Also add a hook for block_read functions Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * | [PATCH 1_4] Merge common get_dev() routines for block devicesGrant Likely2007-02-20-1/+1
| | | | | | | | | | | | | | | | | | | | | Each of the filesystem drivers duplicate the get_dev routine. This change merges them into a single function in part.c Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
| * | Merge with /home/tur/git/u-boot#motionproWolfgang Denk2007-02-16-4/+4
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| | * [Motion-PRO] Preliminary support for the Motion-PRO board.Bartlomiej Sieka2007-02-09-4/+4
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* | | [PATCH] Add support for the AMCC Katmai (440SPe) eval boardStefan Roese2007-02-20-8/+64
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-0/+2943
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Split 4xx SPD SDRAM init routines into 2 filesStefan Roese2007-02-20-413/+478
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the existing 4xx SPD SDRAM initialization routines for the 405 SDRAM controller and the 440 DDR controller don't have much in common this patch splits both drivers into different files. This is in preparation for the 440 DDR2 controller support (440SP/e). Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Add support for multiple I2C bussesStefan Roese2007-02-20-213/+245
|/ / | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for multiple I2C busses on the PPC4xx platforms. Define CONFIG_I2C_MULTI_BUS in the board config file to make use of this feature. It also merges the 405 and 440 i2c header files into one common file 4xx_i2c.h. Also the 4xx i2c reset procedure is reworked since I experienced some problems with the first access on the 440SPe Katmai board. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Correctly display PCI arbiter en-/disabled on some 4xx boardsStefan Roese2007-02-02-6/+10
| | | | | | | | | | | | | | | | Previously the strapping DCR/SDR was read to determine if the internal PCI arbiter is enabled or not. This strapping bit can be overridden, so now the current status is read from the correct DCR/SDR register. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] Update 440EPx/440GRx cpu detectionStefan Roese2007-01-31-4/+8
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | LPC2292 SODIMM port coding style cleanup.Wolfgang Denk2007-01-30-5/+5
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* | Add port for the lpc2292sodimm evaluation board from EmbeddedArtistsGary Jennejohn2007-01-24-3/+174
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* Merge with /home/tur/proj/idmr/u-bootWolfgang Denk2007-01-24-1/+33
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| * [ColdFire MCF5271 family] Add CPU detection based on the value of ChipBartlomiej Sieka2007-01-23-1/+33
| | | | | | | | Identification Register (CIR).
* | Merge with /home/hs/SC3/u-boot-devWolfgang Denk2007-01-19-6/+3
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| * | [PATCH] Fix: Compilerwarnings for SC3 board.Heiko Schocher2007-01-18-6/+3
| | | | | | | | | | | | | | | | | | | | | The EBC Configuration Register is now by CFG_EBC_CFG definable Added JFFS2 support for the SC3 board. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | [PATCH] Add support for AMCC Taishan PPC440GX eval boardStefan Roese2007-01-18-76/+104
|/ / | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/hs/SC3/u-bootWolfgang Denk2007-01-15-6/+15
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| * | Added support for the SOLIDCARD III board from EurodesignHeiko Schocher2007-01-11-2/+7
| | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
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