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* Blackfin: allow serial console to be disabledMike Frysinger2009-01-28-0/+8
| | | | | | | Some devices have no UART device pulled out, so allow people to disable the driver completely in favor of other methods (like JTAG-console). Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: support console-over-JTAGMike Frysinger2009-01-28-4/+130
| | | | | | | The Blackfin JTAG has the ability to pass data via a back-channel without halting the processor. Utilize that channel to emulate a console. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: handle new anomalies with resetMike Frysinger2009-01-28-5/+15
| | | | | | Workaround fun new anomalies related to software reset of the processor. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: pass RETX to LinuxMike Frysinger2009-01-28-0/+6
| | | | | | | Make sure we save the value of RETX at power on and then pass it on to the kernel so that it can nicely debug a "double-fault-caused-a-reset" crash. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: clarify relocation comment during initMike Frysinger2009-01-28-3/+7
| | | | | | | People often ask questions about the init process and when things go from flash to relocated base, so clarify the comments a bit. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: just set SP register directly during initMike Frysinger2009-01-28-3/+2
| | | | | | | No need to set the SP register indirectly to the configured value when it can be set directly. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: add portmuxing for UARTs on the BF51xMike Frysinger2009-01-28-1/+10
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: respect CONFIG_CLKIN_HALFMike Frysinger2009-01-28-1/+1
| | | | | | | | As pointed out by Ivan Koryakovskiy, the initialization code was not actually respecting the CONFIG_CLKIN_HALF option when configuring the PLL_CTL register. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: use common memcpy routine during initMike Frysinger2009-01-28-21/+11
| | | | | | | Rather than using a local custom memcpy function, just call the existing optimized Blackfin version. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: overhaul i2c driverMike Frysinger2009-01-28-429/+1
| | | | | | | | | | | The current Blackfin i2c driver does not work properly with certain devices due to it breaking up transfers incorrectly. This is a rewrite of the driver and relocates it to the newer place in the source tree. Also remove duplicated I2C speed defines in Blackfin board configs and disable I2C slave address usage since it isn't implemented. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: fix dcache handling when doing dma memcpy'sMike Frysinger2009-01-28-2/+2
| | | | | | | | Our dcache invalidate function doesn't just invalidate, it also flushes. So rename the function accordingly and fix the dma_memcpy() function so it doesn't inadvertently corrupt the data destination. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Blackfin: minimize time cache is turned off when replacing cplb entriesMike Frysinger2009-01-28-22/+9
| | | | Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* Command usage cleanupPeter Tyser2009-01-28-4/+4
| | | | | | | | Remove command name from all command "usage" fields and update common/command.c to display "name - usage" instead of just "usage". Also remove newlines from command usage fields. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Standardize command usage messages with cmd_usage()Peter Tyser2009-01-28-8/+8
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mipsWolfgang Denk2009-01-27-0/+28
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| * MIPS: Add flush_dcache_range() and invalidate_dcache_range()Stefan Roese2009-01-27-0/+28
| | | | | | | | | | | | | | | | | | | | This patch adds flush_/invalidate_dcache_range() to the MIPS architecture. Those functions are needed for the upcoming dcache support for the USB EHCI driver. I chose this API because those cache handling functions are already present in the PPC architecture. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* | ppc4xx: Improve DDR autodetectDirk Eibach2009-01-26-5/+50
|/ | | | | | | | | Added support for a second memory bank to DDR autodetection for 440 platforms. Made hardcoded values configurable. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2009-01-24-36/+78
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| * Add secondary CPUs processor frequency for e500 coreHaiying Wang2009-01-23-8/+24
| | | | | | | | | | | | | | | | | | This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
| * fsl-ddr: use the 1T timing as default configurationDave Liu2009-01-23-1/+1
| | | | | | | | | | | | | | | | | | For light loaded system, we use the 1T timing to gain better memory performance, but for some heavily loaded system, you have to add the 2T timing options to board files. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | Some 85xx processors have the advanced power management feature, such as wake up ARP, that needs enable the automatic self refresh. If the DDR controller pass the SR_IT (self refresh idle threshold) idle cycles, it will automatically enter self refresh. However, anytime one transaction is issued to the DDR controller, it will reset the counter and exit self refresh state. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+13
| | | | | | | | | | | | | | | | - The DDR3 controller is expanding the bits for timing config - Add the DDR3 32-bit bus mode support Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
| * fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
| | | | | | | | | | | | | | | | According to the latest 8572 UM, the DDR3 controller is expanding the bit mask, and we use the extend ACTTOPRE mode when tRAS more than 19 MCLK. Signed-off-by: Dave Liu <daveliu@freescale.com>
| * 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-4/+12
| | | | | | | | | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-4/+12
| | | | | | | | | | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* | Merge branch 'master' of git://git.denx.de/u-boot-mpc83xxWolfgang Denk2009-01-24-43/+376
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| * \ Merge branch 'next'Kim Phillips2009-01-23-43/+376
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| | * 83xx: Use the proper sequence for updating IMMR.Scott Wood2009-01-21-3/+15
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This ensures that subsequent accesses properly hit the new window. The dcbi during the NAND loop was accidentally working around this; it's no longer necessary, as the cache is not enabled. Reported-by: Suchit Lepcha <Suchit.Lepcha@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * mpc83xx: Add support for MPC83xx PCI-E controllersAnton Vorontsov2009-01-21-2/+317
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for MPC83xx PCI-E controllers in Root Complex mode. The patch is based on Tony Li and Dave Liu work[1]. Though unlike the original patch, by default we don't register PCI-E buses for use in U-Boot, we only configure the controllers for future use in other OSes (Linux). This is done because we don't have enough of spare BATs to map all the PCI-E regions. To actually use PCI-E in U-Boot, users should explicitly define CONFIG_83XX_GENERIC_PCIE_REGISTER_HOSES symbol in the board file. And only then U-Boot will able to access PCI-E, but at the cost of disabled address translation. [1] http://lists.denx.de/pipermail/u-boot/2008-January/027630.html Signed-off-by: Tony Li <tony.li@freescale.com> Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Acked-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * 83xx: PCI agent mode fixes for multi-board systemsIra Snyder2009-01-21-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | When running a system with 2 or more MPC8349EMDS boards in PCI agent mode, the boards will lock up the PCI bus by scanning against each other. The boards lock against each other by trying to access the PCI bus before clearing their configuration lock bit. Both boards end up in a loop, sending and receiving "Target Not Ready" messages forever. When running in PCI agent mode, the scanning now takes place after the boards have cleared their configuration lock bit. Also, add a missing declaration to the mpc83xx.h header file, fixing a build warning. Signed-off-by: Ira W. Snyder <iws@ovro.caltech.edu> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| | * mpc83xx: Size optimization of start.SRon Madrid2009-01-21-38/+39
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Currently there are in excess of 100 bytes located at the beginning of the image built by start.S that are not being utilized. This patch moves a few functions into this part of the image. This will create a greater number of *available* bytes that can be used by board specific code in NAND builds and will decrease the size of the assembled code in other builds. Signed-off-by: Ron Madrid <ron_madrid@sbcglobal.net> Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | | Remove #ifdef CONFIG_SC520 in source codeGraeme Russ2009-01-24-4/+0
| | | | | | | | | | | | | | | | | | CONFIG_SC520 is now used for conditional compile Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | | Added MMCR reset functionalityGraeme Russ2009-01-24-0/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Reset function specific to AMD SC520 microcontroller - Is more of a 'hard reset' that the triple fault. Requires CONFIG_SYS_RESET_SC520 to be defined in config I would have liked to add this to a new file (cpu/i386/sc520/reset.c) but ld requires that a object file in a library arhive MUST contain at least one function which does not override a weak function (and is called from outside the object file) in order for that object file to be extracted from the archive. This would be the only function on the new file, and hence, will never get linked in. Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | | Moved generic (triple fault) reset codeGraeme Russ2009-01-24-16/+17
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Moved from interrupts.c to cpu.c and made into a weak function to allow vendor specific override Vendor specific CPU reset (like the AMD SC520 MMCR reset) can now be added to the vendor specific code without the need to remember to #undef usage of the generic method and if you forget to include your custom reset method, you will always get the default. Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | | Moved definition of set_vector() to new header fileGraeme Russ2009-01-24-1/+2
| | | | | | | | | | | | | | | | | | | | | This allows for future tidy ups and functionality that will require set_vector () Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | | Renamed cpu/i386/reset.S to resetvec.SGraeme Russ2009-01-24-2/+2
|/ / | | | | | | | | | | | | Brings i386 in line with other CPUs with a reset vector and frees up reset.c for CPU reset functions Signed-off-by: Graeme Russ <graeme.russ@gmail.com>
* | microblaze: Use cache functions (especially cache status)Michal Simek2009-01-23-3/+0
|/ | | | in systems which are configured without flash
* sh: Fix up rsk7203 target for out of tree buildKieran Bingham2009-01-16-8/+13
| | | | | | | Fix up rsk7203 target to build successfully using out-of-tree build. Signed-off-by: Kieran Bingham <kbingham@mpc-data.co.uk> Signed-off-by: Nobuhiro Iwamatsu <iwamatsu@nigauri.org>
* cpu/mpc824x/Makefile: fix warning with parallel buildsWolfgang Denk2009-01-14-1/+1
| | | | | | | | | | Parallel builds would occasionally issue this build warning: ln: creating symbolic link `cpu/mpc824x/bedbug_603e.c': File exists Use "ln -sf" as quick work around for the issue. Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge branch 'master' of /home/wd/git/u-boot/custodiansWolfgang Denk2009-01-14-1/+5
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| * Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang2009-01-13-1/+5
| | | | | | | | | | | | | | So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* | MPC86xx: fix build warningsWolfgang Denk2009-01-12-3/+1
|/ | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* at91rm9200: move define from lowlevel_init to headerJean-Christophe PLAGNIOL-VILLARD2009-01-06-48/+22
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* at91rm9200: rename lowlevel init value to CONFIG_SYS_Jean-Christophe PLAGNIOL-VILLARD2009-01-06-44/+44
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho2008-12-19-44/+55
| | | | | | | | | | | | | | | | | | | | | | | Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* mpc86xx: Double local bus clock dividerTrent Piepho2008-12-19-0/+1
| | | | | | | | The local bus clock divider should be doubled for both 8610 and 8641. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* mpc8568: Double local bus clock dividerTrent Piepho2008-12-19-2/+2
| | | | | | | | | | | | | The clock divider for the MPC8568 local bus should be doubled, like the other newer MPC85xx chips. Since there are now more chips with a 2x divider than a 1x, and any new 85xx chips will probably be 2x, invert the sense of the #if so that it lists the 1x chips instead of the 2x ones. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: Fix the boot window issueDave Liu2008-12-19-8/+8
| | | | | | | | | | | | | | | | | | | | | | If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Set IVPR to kenrel entry point in second core boot pageHaiying Wang2008-12-19-0/+1
| | | | | | | | | | | Assuming the OSes exception vectors start from the base of kernel address, and the kernel physical starting address can be relocated to an non-zero address. This patch enables the second core to have a valid IVPR for debugger before kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid value for second core which runs kernel at different physical address other than 0x0. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-2/+2
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
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