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* Add denali_data_eye.o and denali_spd_ddr2.o to PPC4xx MakefileLarry Johnson2007-12-27-0/+2
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Add 440EPx DDR2 SPD DIMM supportLarry Johnson2007-12-27-0/+1254
| | | | | | | | | | | | | This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: Larry Johnson <lrj@acm.org>
* Copy 440EPx/GRx SDRAM data-eye search to common directoryLarry Johnson2007-12-27-0/+396
| | | | | | | | This patch creates a non-board-specific file for performing the SDRAM data-eye search. It also adds ECC error checking to the test of valid data on readback when ECC is enabled. Signed-off-by: Larry Johnson <lrj@acm.org>
* Add Ethernet 1000BASE-X support for PPC4xxLarry Johnson2007-12-27-52/+114
| | | | | | | | | | This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG". When this symbol is defined, the PHY will advertise it's capabilities for autonegotiation based on the capabilities shown in the PHY's status registers, including 1000BASE-X. When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will advertise hard-coded capabilities, as before. Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: fdt: Cleanup setup of cpu node setupStefan Roese2007-12-27-3/+4
| | | | | | | | | Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: Stefan Roese <sr@denx.de>
* Fix ppc4xx clear_bss() codeAnatolij Gustschin2007-12-27-4/+13
| | | | | | | | ppc4xx clear_bss() fails if BSS segment size is not divisible by 4 without remainder. This patch provides fix for this problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* PPC4xx: Minimal changes to add vxWorks supportNiklaus Giger2007-12-27-1/+5
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: fix flush + invalidate_dcache_range argumentsMatthias Fuchs2007-12-27-3/+3
| | | | | | | flush + invalidate_dcache_range() expect the start and stop+1 address. So the stop address is the first address behind (!) the range. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: fdt: use fdt_fixup_ethernet()Stefan Roese2007-12-27-71/+2
| | | | | | | | | By using aliases in the dts file, the ethernet node fixup is much easier with the recently added functions. Please note that the dts file needs the aliases for this to work. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Bring 4xx fdt support up-to-dateStefan Roese2007-12-27-80/+34
| | | | | | | | This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correct GPIO offset in gpio_config()Stefan Roese2007-12-11-1/+1
| | | | | | Thanks to Gary Jennejohn for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correct 405EX PCIe UTL register mappingStefan Roese2007-11-18-3/+3
| | | | | | Map 4k mem space for UTL registers for each port. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 405EX PCIe UTL register configurationStefan Roese2007-11-16-4/+42
| | | | | | | | Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-78/+62
| | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 405EX PCIe UTLSET register setupStefan Roese2007-11-13-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make USB working with CONFIG_4xx_DCACHE definedMatthias Fuchs2007-11-09-1/+17
| | | | | | | | | | This patch disables the 44x d-cache on 'usb start' and reenables it on 'usb stop'. This should be seen as a temporary fix until the generic usb-ohci driver can life with d-cache enabled. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove redundant code from 4xx network driverMatthias Fuchs2007-11-09-5/+3
| | | | | | | | This patch removes some redundant code and decrements the end address of cache flush and invalidate by 1. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make output a little shorter on I2C bootrom detectionStefan Roese2007-11-09-34/+19
| | | | | | | | | | | Most 4xx PPC capable of using an I2C bootrom for bootstrap setting already print a line with the information which I2C bootrom is used for bootstrap configuration. So we don't need this extra line with "I2C boot EEPROM en-/dis-abled". This patch also has a little code cleanup integrated. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-8/+5
| | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change 4xx ethernet driver to handle cached memory tooStefan Roese2007-10-31-75/+62
| | | | | | | This patch enables the 4xx EMAC driver to work too, when dcache is enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add change_tlb function to modify I attribute of TLB(s)Stefan Roese2007-10-31-1/+87
| | | | | | | This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rework 4xx cache supportStefan Roese2007-10-31-135/+290
| | | | | | | New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change autonegotiation timeout from 4 to 5 secondsStefan Roese2007-10-31-1/+1
| | | | | | | | I lately noticed, that newer 4xx board with GBit support sometimes don't finish link autonegotiation in 4 seconds. Changing this timeout to 5 seconds seems fine here. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friendsStefan Roese2007-10-31-73/+74
| | | | | | | This patch changes all in32/out32 calls to use the recommended in_be32/ out_be32 macros instead. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correct UART input clock calculation and passing to fdtStefan Roese2007-10-31-5/+7
| | | | | | | | We now use a value in the gd (global data) structure for the UART input frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely in get_sys_info(). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial AMCC Haleakala PPC405EXr eval board supportStefan Roese2007-10-31-0/+10
| | | | | | | | | | The Haleakala is nearly identical with the Kilauea eval board. The only difference is that the 405EXr only supports one EMAC and one PCIe interface. This patch adds support for the Haleakala board by using the identical image for Kilauea and Haleakala. The distinction is done by comparing the PVR. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rework of 4xx serial driver (4)Stefan Roese2007-10-31-167/+146
| | | | | | | | | | | | Change 4xx_uart.c: - Use in_8/out_8 macros instead of in8/out8 - No need for UART_BASE marco anymore, now really handled via function parameter - serial_init_common() introduced - Further coding style cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rework of 4xx serial driver (1)Stefan Roese2007-10-31-208/+243
| | | | | | | | | This patch starts the rework of the PPC4xx serial driver. First we split the file into two seperate files, one 4xx_uart.c with the 405/440 UART handling code and the other one iop480_uart.c with the UART code for the PLX-Tech IOP480 PPC (PPC403 based). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correct UART input clock calculation and passing to fdtStefan Roese2007-10-31-4/+15
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add freqUART to CPU speed detectionStefan Roese2007-10-31-8/+24
| | | | | | | This value is needed later for the device tree configuration of the uart clock. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xxStefan Roese2007-10-31-34/+31
| | | | | | | | | | This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add PCIe endpoint support on Kilauea (405EX)Stefan Roese2007-10-31-10/+21
| | | | | | | | | | | | This patch adds endpoint support for the AMCC Kilauea eval board. It can be tested by connecting a reworked PCIe cable (only 1x lane singles connected) to another root-complex. In this test setup, a 64MB inbound window is configured at BAR0 which maps to 0 on the PLB side. So accessing this BAR0 from the root-complex will access the first 64MB of the SDRAM on the PPC side. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint modeStefan Roese2007-10-31-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add additional debug info to 4xx fdt supportStefan Roese2007-10-31-0/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix small merge problem in 4xx_enet.cStefan Roese2007-10-31-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add PPC405EX supportStefan Roese2007-10-31-100/+532
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Cleanup of 4xx PCI and PCIe support (renaming)Stefan Roese2007-10-31-0/+11
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial fdt support to 4xx (first needed on 405EX)Stefan Roese2007-10-31-0/+171
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Change PCIe status output to match common styleStefan Roese2007-10-31-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Disable debug output as defaultStefan Roese2007-10-31-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support addedStefan Roese2007-10-31-39/+54
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & KatmaiStefan Roese2007-10-31-1/+24
| | | | | | | | | | | | | | | | | 128MB seems to be the smallest possible value for the memory size for on PCIe port. With this change now the BAR's of the PCIe cards are accessible under U-Boot. One big note: This only works for PCIe port 0 & 1. For port 2 this currently doesn't work, since the base address is now 0xc0000000 (0xb0000000 + 2 * 0x08000000), and this is already occupied by CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean to change the base addresses completely and this change would have too much impact right now. This patch adds debug output to the 4xx pcie driver too. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idxStefan Roese2007-10-31-6/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rename 405gp_pci to 4xx_pci since its used on all 4xx platformsStefan Roese2007-10-31-4/+4
| | | | | | | | These files were introduced with the IBM 405GP but are currently used on all 4xx PPC platforms. So the name doesn't match the content anymore. This patch renames the files to 4xx_pci.c/h. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add a comment for 405EX PCIe endpoint configurationStefan Roese2007-10-31-0/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)Stefan Roese2007-10-31-419/+223
| | | | | | | | | | | | | | | (3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access the SDR registers of the PCIe ports. This makes the overall design clearer, since it removed a lot of switch statements which are not needed anymore. Also, the functions ppc4xx_init_pcie_rootport() and ppc4xx_init_pcie_entport() are merged into a single function ppc4xx_init_pcie_port(), since most of the code was duplicated. This makes maintainance and porting to other 4xx platforms easier. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)Stefan Roese2007-10-31-10/+10
| | | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)Stefan Roese2007-10-31-178/+3
| | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Coding style cleanupStefan Roese2007-10-02-12/+12
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Program EPLD to force full duplex mode for PHY.Grzegorz Bernacki2007-10-02-4/+8
| | | | | | | EPLD forces modes of PHY operation. By default full duplex is turned off. This fix turns it on. Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com>
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