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* ppc4xx: Reorganize DDR2 ECC handlingFelix Radensky2009-10-02-207/+249
| | | | | | | | | | Reorganize DDR2 ECC handling to use common code for SPD DIMMs and soldered SDRAM. Also, use common code to display SDRAM info (ECC, CAS latency) for SPD and soldered SDRAM variants. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove mtsdram0() marcos and use common mtsdram() insteadStefan Roese2009-09-28-14/+13
| | | | | | Additionally some whitespace coding style fixes. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Convert PPC4xx SDRAM defines from lower case to upper caseStefan Roese2009-09-28-65/+65
| | | | | | | | | The latest PPC4xx register cleanup patch missed some SDRAM defines. This patch now changes lower case UIC defines to upper case. Also some names are changed to match the naming in the IBM/AMCC users manuals (e.g. mem_mcopt1 -> SDRAM0_CFG). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Convert PPC4xx UIC defines from lower case to upper caseStefan Roese2009-09-28-14/+14
| | | | | | | The latest PPC4xx register cleanup patch missed the UIC defines. This patch now changes lower case UIC defines to upper case. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix PCIE PLL lock on 440SPe Yucca boardRupjyoti Sarmah2009-09-23-8/+15
| | | | | | | | | | u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of the PLL lock. Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate get_OPB_freq()Stefan Roese2009-09-17-75/+15
| | | | | | | | | | | | | All 4xx variants had their own, mostly identical get_OPB_freq() function. Some variants even only had the OPB frequency calculated in this routine and not supplied the sys_info.freqOPB variable correctly (e.g. 405EZ). This resulted in incorrect OPB values passed via the FDT to Linux. This patch now removes all those copies and only uses one function for all 4xx variants (except for IOP480 which doesn't have an OPB). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 405EZ uart base baud calculationStefan Roese2009-09-17-1/+5
| | | | | | | With this fix, Linux correctly configures the baudrate when booting with FDT passed from U-Boot to Linux. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Big cleanup of PPC4xx definesStefan Roese2009-09-11-171/+171
| | | | | | | | | | | | | | | | This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix compilation warning in 4xx miiphy.cStefan Roese2009-09-10-1/+1
| | | | | | | | | | This patch fixes the following compilation warning: miiphy.c: In function 'emac4xx_miiphy_read': miiphy.c:353: warning: dereferencing type-punned pointer will break strict-aliasing rules Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Allow overwriting pci target registers for all 4xx boardsMatthias Fuchs2009-09-10-2/+2
| | | | | | | | | | | | | This patch adds the CONFIG_PCI_4xx_PTM_OVERWRITE option and replaces the ugly 'if defined(BOARD1) || ... || defined(BOARDn)' construct in 4xx pci code. When CONFIG_PCI_4xx_PTM_OVERWRITE is defined the default ptm register setup can be overwritten through environment variables ptm1la, ptm1ms, ptm2la and ptm2ms to do application specific pci target BAR configuration. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc: Remove -fno-strict-aliasingKumar Gala2009-09-04-1/+1
| | | | | | -fno-strict-aliasing is hidding warnings. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Dual-license IBM code contributionsJosh Boyer2009-08-09-0/+9
| | | | | | | | | | | | | It was brought to our attention that U-Boot contains code derived from the IBM OpenBIOS source code originally provided with some of the older PowerPC 4xx development boards. As a result, the original license of this code has been carried in the various files for a number of years in the U-Boot project. IBM is dual-licensing the IBM code contributions already present in U-Boot under either the terms of the GNU General Public License version 2, or the original code license already present. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* ppc4xx: Add basic support for AMCC PPC460EX/460GT rev B chipsStefan Roese2009-07-30-0/+23
| | | | | | | This patch is based on a diff created by Phong Vo from AMCC. Signed-off-by: Phong Vo <pvo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Replace 4xx lowercase SPR referencesMatthias Fuchs2009-07-24-118/+119
| | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* Add "chip_config" command for PPC4xx bootstrap configurationStefan Roese2009-07-24-0/+145
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds a generic command for programming I2C bootstrap eeproms on PPC4xx. An implementation for Canyonlands board is included. The command name is intentionally chosen not to be PPC4xx specific. This way other CPU's/SoC's can implement a similar command under the same name, perhaps with a different syntax. Usage on Canyonlands: => chip_config Available configurations (I2C address 0x52): 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 600-nand - NAND CPU: 600 PLB: 200 OPB: 100 EBC: 100 800-nor - NOR CPU: 800 PLB: 200 OPB: 100 EBC: 100 800-nand - NAND CPU: 800 PLB: 200 OPB: 100 EBC: 100 1000-nor - NOR CPU:1000 PLB: 200 OPB: 100 EBC: 100 1000-nand - NAND CPU:1000 PLB: 200 OPB: 100 EBC: 100 1066-nor - NOR CPU:1066 PLB: 266 OPB: 88 EBC: 88 *** 1066-nand - NAND CPU:1066 PLB: 266 OPB: 88 EBC: 88 => chip_config 600-nor Using configuration: 600-nor - NOR CPU: 600 PLB: 200 OPB: 100 EBC: 100 done (dump via 'i2c md 52 0.1 10') Reset the board for the changes to take effect Other 4xx boards will be migrated to use this command soon as well. Signed-off-by: Stefan Roese <sr@denx.de> Signed-off-by: Dirk Eibach <eibach@gdsys.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd.eu>
* ppc4xx: Fix missing freqOPB for 405EPDirk Eibach2009-07-24-0/+2
| | | | | | | | In cpu/ppc4xx/speed.c initialization of sysInfo->freqOPB for 405EP was left out for no obvious reason. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix TLB reset problem with recent 44x imagesStefan Roese2009-07-24-2/+7
| | | | | | | | | | | | | | | | | Patch d873133f [ppc4xx: Add Sequoia RAM-booting target] broke "normal" booting on some 44x platforms. This breakage is only noticed in some cases while powercycling. As it seems, the code in question in start.S didn't invalidate TLB #0. This makes sense since this TLB is used for the bootrom mapping. With the patch mentioned above even TLB #0 got invalidated resulting in an error later on. This patch now fixes this issue by only invalidating TLB #0 in the RAM- booting case. Tested succesfully on Sequoia and Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <Eibach@gdsys.de>
* nand/ppc4xx: Move PPC4xx NAND driver to common NAND driver directoryStefan Roese2009-07-16-224/+0
| | | | | | Signed-off-by: Stefan Roese <sr@denx.de> Cc: Scott Wood <scottwood@freescale.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
* ppc4xx: Set default PCI device ID for 405EP boardsMatthias Fuchs2009-07-10-2/+9
| | | | | | | | | | | | | Current code only sets the PCI vendor id to 0x1014 and leaved device id to 0x0000. Ths patch .... a) uses the correct PCI_VENDOR_ID_IBM macro for this b) sets the default device ID as stated in the UM to 0x0156 by using PCI_DEVICE_ID_IBM_405GP for this. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()Matthias Fuchs2009-07-10-5/+14
| | | | | | | | | | | | | | | | | | | | This patch moves some basic PCI initialisation from the 4xx cpu_init_f() to cpu/ppc4xx/4xx_pci.c. The original cpu_init_f() function enabled the 405EP's internal arbiter in all situations. Also the HCE bit in cpc0_pci is always set. The first is not really wanted for PCI adapter designs and the latter is a general bug for PCI adapter U-Boots. Because it enables PCI configuration by the system CPU even when the PCI configuration has not been setup by the 405EP. The one and only correct place is in pci_405gp_init() (see "Set HCE bit" comment). So for compatibility reasons the arbiter is still enabled in any case, but from weak pci_pre_init() so that it can be replaced by board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make pll_write globalMatthias Fuchs2009-07-08-0/+1
| | | | | | | | | | | | | | This patch makes pll_write on PPC405EP boards global and callable from C code. pll_write can be used to dynamically modify the PLB:PCI divider as it is required for 33/66 MHz pci adapters based on the 405EP. board_early_init_f() is a good place to do that (check M66EN signal and call pll_write() when it is required). Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove compilation warning "pci_async_enabled defined but not used"Stefan Roese2009-07-08-0/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Implement is_pci_host() for 405 CPUsMatthias Fuchs2009-07-08-3/+16
| | | | | | | | | | | | | | | | | | | This patch implements the is_pci_host() function in a similiar way as it is used on 440 targets. The former path with CONFIG_PCI_HOST == PCI_HOST_AUTO does not build on 405EP targets because checking the PCI arbiter is different. So putting the fixed code into a separate function makes the code more readable. Also using is_pci_host() on 405 brings 405 and 440 PCI code a little bit closer. In preparation for an upcoming 405EP based PMC module I made this function weak so that it can be overwritten from board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fixed PPC4xx debug compilation error in uic.cAlessio Centazzo2009-07-08-1/+1
| | | | | | | | | | This patch fixes a debug compilation error for PPC4xx platforms, all other architectures are not affected by this change. The 'handler' pointer was undefined. The fix is exercised and has effect only if DEBUG is defined. Signed-off-by: Alessio Centazzo acpatin@yahoo.com Signed-off-by: Stefan Roese <sr@denx.de>
* 4xx: Fix compilation warnings and MQ registers dump in SPD DDR2 codeFelix Radensky2009-07-08-17/+25
| | | | | | | | | | This patch fixes printf format string compilation warnings in several debug statements. It also fixes the dump of DDR controller MQ registers found on some 44x and 46x platforms. The current register dump code uses incorrect DCRs to access these registers. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove PCI async bootup message if PCI is not usedStefan Roese2009-06-12-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Sequoia RAM-booting targetStefan Roese2009-06-12-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
* i2c: Create common default i2c_[set|get]_bus_speed() functionsPeter Tyser2009-06-12-14/+0
| | | | | | | | | | | | | New default, weak i2c_get_bus_speed() and i2c_set_bus_speed() functions replace a number of architecture-specific implementations. Also, providing default functions will allow all boards to enable CONFIG_I2C_CMD_TREE. This was previously not possible since the tree-form of the i2c command provides the ability to display and modify the i2c bus speed which requires i2c_[set|get]_bus_speed() to be present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* i2c.h: Provide a default CONFIG_SYS_I2C_SLAVE valuePeter Tyser2009-06-12-8/+0
| | | | | | | | Many boards/controllers/drivers don't support an I2C slave interface, however CONFIG_SYS_I2C_SLAVE is used in common code so provide a default Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Fix problem with ECC ordering for PPC4xx NDFC platformsStefan Roese2009-05-23-2/+2
| | | | | | | | | | | | | This patch now uses the correct ECC byte order (Smart Media - SMC) to be used on the 4xx NAND FLASH driver. Without this patch we have incompatible ECC byte ordering to the Linux kernel NDFC driver. Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in drivers/mtd/nand/nand_ecc.c for correct operation. This is done with a seperate patch. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* ppc4xx: Move definition for PPC4xx NAND FLASH controller to headerStefan Roese2009-05-23-6/+3
| | | | | | | | | This patch moves the definition for the PPC4xx NAND FLASH controller (NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the upcoming fix for the ECC byte ordering of the NDFC driver. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* Fix e-mail address of Gary Jennejohn.Detlev Zundel2009-05-15-1/+1
| | | | Signed-off-by: Detlev Zundel <dzu@denx.de>
* Replace __attribute references with __attribute__Peter Tyser2009-04-28-4/+4
| | | | | | | | __attribute__ follows gcc's documented syntax and is generally more common than __attribute. This change is only asthetic and should not affect functionality. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Add "booting from NAND" to 4xx NAND-booting targetsStefan Roese2009-04-16-1/+5
| | | | | | | | This additional text in the bootup log helps to see if the board is configured for NAND-booting. Especially helpful for boards that can boot from NOR and NAND (e.g. most of the AMCC eval boards). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Don't write the MAC address into the internal SoC registersStefan Roese2009-03-20-28/+1
| | | | | | | Remove this code. It's not needed. The 4xx EMAC driver stores the MAC addresses into the SoC registers instead. Signed-off-by: Stefan Roese <sr@denx.de>
* cpu/: get mac address from environmentMike Frysinger2009-03-20-6/+8
| | | | | | | | | | | | | | | | | | | The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. The cpus that get converted here: at91rm9200 mpc512x mpc5xxx mpc8260 mpc8xx ppc4xx Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com> CC: John Rigby <jrigby@freescale.com> CC: Stefan Roese <sr@denx.de>
* ppc4xx: Fix bug in PCI outbound map configuration for canyonlandsAnatolij Gustschin2009-03-20-2/+4
| | | | | | | | | | | | | | PCI outbound address map configuration doesn't match the PCI memory address range covered by appropriate TLB entry configuration for canyonlands causing machine check exceptions while accessing PCI memory regions. This patch provides a fix for this issue. Kazuaki Ichinohe observed and reported this issue while testing display output with PCI ATI video card on canyonlands. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: PCIe: Change 16GB inbound memory to 4GBStefan Roese2009-02-18-2/+2
| | | | | | | This patch fixes a problem recently seen on some 4xx platforms. For example on Kilauea PCIe slot #0. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix initialization of the SDRAM_CODT registerCarolyn Smith2009-02-12-5/+2
| | | | | | | | | This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2 initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits. Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Autocalibration can set RDCC to over aggressive value.Adam Graham2009-02-12-29/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc: Move CONFIG_MAX_MEM_MAPPED to common config.hKumar Gala2009-02-10-3/+0
| | | | | | | | Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent between the two current users (lib_ppc/board.c, 44x SPD DDR2). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarityKumar Gala2009-02-07-2/+2
| | | | | | | | | | The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Make PCIE support selectableDirk Eibach2009-02-06-3/+4
| | | | | | | | | On some platforms PCIE support is not required, but would be included because the cpu supports it. To reduce fooprint it is now configurable via CONFIG_PCI_DISABLE_PCIE. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Only fixup opb attached UARTsMatthias Fuchs2009-02-06-2/+22
| | | | | | | | | This patch updates the fdt UART clock fixup code to only touch CPU internal UARTs on 4xx systems. Only these UARTs are definitely clocked by gd->uart_clk. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Standardize command usage messages with cmd_usage()Peter Tyser2009-01-28-2/+2
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Improve DDR autodetectDirk Eibach2009-01-26-5/+50
| | | | | | | | | Added support for a second memory bank to DDR autodetection for 440 platforms. Made hardcoded values configurable. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanup, update CHANGELOG.Wolfgang Denk2008-12-16-2/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functionsTimur Tabi2008-12-15-20/+0
| | | | | | | | | | All implementations of the functions i2c_reg_read() and i2c_reg_write() are identical. We can save space and simplify the code by converting these functions into inlines and putting them in i2c.h. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Section name should be ".data", not "data"Trent Piepho2008-12-09-4/+3
| | | | | Signed-off-by: Trent Piepho <tpiepho@freescale.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-1/+2
| | | | | | | Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
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