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* Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-07-16-1/+1
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| * Update CHANGELOG, minor coding style cleanup.Wolfgang Denk2007-07-12-1/+1
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc4xx: Code cleanupStefan Roese2007-07-16-1/+0
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add new weak functions to support boardspecific DDR2 configurationStefan Roese2007-07-16-14/+44
| | | | | | | | | | | | | | The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better support non default, boardspecific DDR(2) controller configuration. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add remove_tlb() function to remove a mem area from TLB setupStefan Roese2007-07-16-1/+61
| | | | | | | | | | | | | | | | | | | | The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Change receive buffer handling in the 4xx emac driverStefan Roese2007-07-12-3/+5
|/ | | | | | | This change fixes a bug in the receive buffer handling, that could lead to problems upon high network traffic (broadcasts...). Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanup; update CHANGELOG.Wolfgang Denk2007-07-10-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge with /home/hs/Atronic/u-bootWolfgang Denk2007-07-09-41/+61
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| * [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANGHeiko Schocher2007-06-25-53/+58
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * [PCS440EP] upgrade the PCS440EP board:Heiko Schocher2007-06-22-41/+56
| | | | | | | | | | | | | | | | | | | | | | | | - Show on the Status LEDs, some States of the board. - Get the MAC addresses from the EEProm - use PREBOOT - use the CF on the board. - check the U-Boot image in the Flash with a SHA1 checksum. - use dynamic TLB entries generation for the SDRAM Signed-off-by: Heiko Schocher <hs@denx.de>
* | Merged POST framework with the current TOT.Sergei Poselenov2007-07-05-0/+8
| | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-25-5/+7
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| * | Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-5/+5
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| * | Extend POST support for PPC440Igor Lisitsin2007-06-22-0/+2
| | | | | | | | | | | | | | | | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* | | ppc4xx: PPC440EPx Emit DDR0 registers on machine check interruptNiklaus Giger2007-06-25-1/+86
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch prints the DDR status registers upon machine check interrupt on the 440EPx/GRx. This can be useful especially when ECC support is enabled. I added some small changes to the original patch from Niklaus to make it compile clean. Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Fix O=buildir buildsNiklaus Giger2007-06-25-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | This patch fixes the problem to assemble cpu/ppc4xx/start.S experienced last week where building failed having specified O=../build.sequoia. Signed-off-by: Niklaus Giger <niklaus.giger@nestal.com>
* | | ppc4xx: Add pci_pre_init() for 405 boardsMatthias Fuchs2007-06-25-8/+22
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for calling a plattform dependant pci_pre_init() function for 405 boards. This can be used to move the current pci_405gp_fixup_irq() function into the board code. This patch also makes the CFG_PCI_PRE_INIT define obsolete. A default function with 'weak' attribute is used when a board specific pci_pre_init() is not implemented. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | ppc4xx: Fix problem with extended program_tlb() funtionStefan Roese2007-06-22-0/+8
|/ / | | | | | | | | | | | | | | | | The recently extended program_tlb() function had a problem when multiple TLB's had to be setup (for example with 512MB of SDRAM). The virtual address was not incremented. This patch fixes this issue and is tested on Katmai with 512MB SDRAM. Signed-off-by: Stefan Roese <sr@denx.de>
* | [ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski2007-06-22-1/+0
| | | | | | | | | | - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
* | Coding style cleanup. Refresh CHANGELOG.Wolfgang Denk2007-06-20-138/+137
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* | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-06-20-1/+1
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| * Fix config problems on SC3 board; make ide_reset_timeout work.Wolfgang Denk2007-06-08-1/+1
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* | [ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese2007-06-19-3/+3
| | | | | | | | | | | | | | | | The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/stefan/git/u-boot/denx-440-exceptionsStefan Roese2007-06-15-204/+242
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| * | ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki2007-06-15-204/+242
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | [ppc4xx] Extend 44x GPIO setup with default output stateStefan Roese2007-06-15-0/+38
| | | | | | | | | | | | | | The board config array CFG_440_GPIO_TABLE for the ppc440 GPIO setup is extended with the default GPIO output state (level). Signed-off-by: Stefan Roese <sr@denx.de>
* | [ppc4xx] Extend program_tlb() with virtual & physical addressesStefan Roese2007-06-14-37/+48
| | | | | | | | | | | | | | | | | | Now program_tlb() allows to program a TLB (or multiple) with different virtual and physical addresses. With this change, now one physical region (e.g. SDRAM) can be mapped 2 times, once with caches diabled and once with caches enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* | [PATCH] fix gpio setting when using CFG_440_GPIO_TABLEBenoît Monin2007-06-08-2/+2
|/ | | | | | | | Set the correct value in GPIOx_TCR when configuring the gpio with CFG_440_GPIO_TABLE. Signed-off-by: Benoit Monin <bmonin@adeneo.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-06-17/+55
| | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Fix ppc4xx bootstrap letter displayed on startupBenoît Monin2007-06-04-1/+7
| | | | | | | | | | | | The attached patch is mainly cosmetic, allowing u-boot to display the correct bootstrap option letter according to the datasheets. The original patch was extended with 405EZ support by Stefan Roese. Signed-off-by: Benoit Monin <bmonin@adeneo.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-287/+349
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| * ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval boardStefan Roese2007-06-01-92/+129
| | | | | | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
| * NAND: Add hardware ECC support to the PPC4xx NAND driver ndfc.cStefan Roese2007-06-01-20/+54
| | | | | | | | | | | | | | | | | | | | This patch adds hardware ECC support to the NDFC driver. It also changes the register access from using the "simple" in32/out32 functions to the in_be32/out_be32 functions, which make sure that the access is correctly synced. This is the only recommended access to SoC registers in the current Linux kernel. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: 44x DDR driver code cleanup and small fix for BambooStefan Roese2007-06-01-175/+166
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-06-01-1/+6
| | | | | | | | | | | | | | Add config option for 180 degree advance clock control as needed for the AMCC Luan eval board. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add 405 support to 4xx NAND driver ndfc.cStefan Roese2007-05-22-4/+4
| | | | | | | | | | | | | | This patch adds support for 405 PPC's to the 4xx NAND driver ndfc.c. This is in preparation for the new AMCC 405EZ. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix problem in 405EZ OCM initializationStefan Roese2007-05-21-1/+1
| | | | | | | | | | | | | | As spotted by Bruce Adler this patch fixes an initialization problem for the 405EZ OCM. Signed-off-by: Stefan Roese <sr@denx.de>
* | Coding stylke cleanup; update CHANGELOG.Wolfgang Denk2007-05-05-2/+2
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-04-29-28/+28
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| * Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xxWolfgang Denk2007-04-18-28/+28
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| | * Merge with /home/git/u-bootWolfgang Denk2007-03-08-26/+40
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| | * \ Merge with /home/git/u-bootWolfgang Denk2007-03-08-4/+27
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| | * | | Some code cleanup.Wolfgang Denk2007-03-04-41/+41
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* | | | | ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.Matthias Fuchs2007-04-24-9/+21
|/ / / / | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | | ppc4xx: Add output for bootrom location to 405EZ portsStefan Roese2007-04-18-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now 405EZ ports also show upon bootup from which boot device they are configured to boot: U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) Bootstrap Option E - Boot ROM Location EBC (32 bits) 16 kB I-Cache 16 kB D-Cache Board: Acadia - AMCC PPC405EZ Evaluation Board Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: Fix i2c divisor calcularion for PPC4xxJeffrey Mann2007-04-12-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes changes the i2c_init(...) function to use the function get_OPB_freq() rather than calculating the OPB speed by sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is specific per processor. The prior method was not and so was calculating the wrong speed for some PPC4xx processors. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-03-31-19/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Additional RAM information is now printed upon powerup, like DDR2 frequency and CAS latency. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-03-31-48/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a bug in the auto calibration routine. This driver now runs more reliable with the tested modules. It's also tested with 167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-156/+226
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| * | | | [PATCH] Add 4xx GPIO functionsStefan Roese2007-03-24-114/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese <sr@denx.de>
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