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* ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initializationDave Mitchell2008-11-21-7/+20
| | | | | | | | | | | | | | | | | | Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRsDave Mitchell2008-11-21-20/+21
| | | | | | | | | | | Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header. Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Clear all potentially pending exceptions in MCSRStefan Roese2008-11-20-0/+4
| | | | | | | | This is needed on Canyonlands which still has an exception pending while running relocate_code(). This leads to a failure after trap_init() is moved to the top of board_init_r(). Signed-off-by: Stefan Roese <sr@denx.de>
* Moved initialization of PPC4xx EMAC to cpu_eth_init()Ben Warren2008-11-09-0/+14
| | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* Moved PPC4xx EMAC driver to drivers/netBen Warren2008-11-09-2128/+0
| | | | | | | Also changed path in all linker scripts that reference this driver Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMACBen Warren2008-11-09-9/+1
| | | | | | | All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx: Generic architecture for xilinx ppc405(v3)Ricardo Ribalda Delgado2008-10-24-1/+2
| | | | | | | | | | | | | | | | | As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-36/+99
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| * ppc4xx: Correctly setup ranges property in ebc nodeStefan Roese2008-10-21-17/+28
| | | | | | | | | | | | | | | | Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add routine to retrieve CPU numberAdam Graham2008-10-21-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add static support for 44x IBM SDRAM ControllerAdam Graham2008-10-21-18/+53
| | | | | | | | | | | | | | | | | | | | This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-3/+3
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge git://git.denx.de/u-boot into x1Markus Klotzbuecher2008-10-21-521/+544
|\ \ | |/ | | | | | | | | Conflicts: drivers/usb/usb_ohci.c
| * Merge 'next' branchWolfgang Denk2008-10-18-517/+517
| |\ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-517/+517
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | ppc4xx: PPC44x MQ initializationYuri Tikhonov2008-10-17-4/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Comment from Stefan: This patch doesn't change the resulting value of the MQ registers. It explicitly sets/clears all bits to the desired state which better documents the resulting register value instead of relying on pre-set default values. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR changeAdam Graham2008-10-08-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | After changing SDRAM_CLKTR phase value rerun the memory preload initialization sequence (INITPLR) to reset and relock the memory DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects the phase relationship of the internal, to the PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * Revert "ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)"Stefan Roese2008-09-22-0/+5
| | | | | | | | | | | | This reverts commit 3eec160a3a405b29ce9c06920f6427b9047dd8a8. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)Victor Gallardo2008-09-16-5/+0
| | | | | | | | | | | | Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | The PIPE_INTERRUPT flag is used wrongRemy Bohmer2008-10-14-4/+4
|/ | | | | | | | | | | | | | At a lot of places in the code the PIPE_INTERRUPT flags and friends are used wrong. The wrong bits are compared to this flag resulting in wrong conditions. Also there are macros that should be used for PIPE_* flags. This patch tries to fix them all, however, I was not able to test the changes, because I do not have any of these boards. Review required! Signed-off-by: Remy Bohmer <linux@bohmer.net> Signed-off-by: Markus Klotzbuecher <mk@denx.de>
* ppc4xx: Fix SDRAM inititialization of multiple 405 based board portsStefan Roese2008-09-12-4/+10
| | | | | | | | | | | | | | | This patch fixes a problem introdiced with patch bbeff30c [ppc4xx: Remove superfluous dram_init() call or replace it by initdram()]. The boards affected are: - PCI405 - PPChameleonEVB - quad100hd - taihu - zeus Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove CONFIG_CS8952_PHY defineStefan Roese2008-09-08-2/+0
| | | | | | | | Since this define is only used on one board that was never really in production, removing this compile time option doesn't hurt and makes the code more readable. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix compilation warning for PIP405Stefan Roese2008-09-08-6/+5
| | | | | | | | | | This patch fixes a compilation warning for the PIP405 board. It moves the #ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't occur anymore. I am a little unsure if this #ifdef is at the correct place now or if it could be removed completely. This needs to get tested on the PIP405 board. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix compilation warning for canyonlands & glacierStefan Roese2008-09-08-7/+3
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add support for GPCS, SGMII and M88E1112 PHYVictor Gallardo2008-09-05-5/+195
| | | | | | | | This patch adds GPCS, SGMII and M88E1112 PHY support for the AMCC PPC460GT/EX processors. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routinesAdam Graham2008-09-05-63/+98
| | | | | Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: IBM Memory Controller DDR autocalibration routinesAdam Graham2008-09-05-0/+1212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alternate SDRAM DDR autocalibration routine that can be generically used for any PPC4xx chips that have the IBM SDRAM Controller core allowing for support of more DIMM/memory chip vendors and gets the DDR autocalibration values which give the best read latency performance (SDRAM0_RDCC.[RDSS]). Two alternate SDRAM DDR autocalibration algoritm are provided in this patch, "Method_A" and "Method_B". DDR autocalibration Method_A scans the full range of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a lot longer to run than Method_B. Method_B executes in the same amount of time as the currently existing DDR autocalibration routine, i.e. 1 second or so. Normally Method_B is used and it is set as the default method. The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_RQDC.[RQFD] 2) SDRAM0_RFDC.[RFFD] This alternate PPC4xx DDR autocalibration code calibrates the following IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_WRDTR.[WDTR] 2) SDRAM0_CLKTR.[CKTR] 3) SDRAM0_RQDC.[RQFD] 4) SDRAM0_RFDC.[RFFD] and will also use the calibrated settings of the above four registers that produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS] register.[bit-field]. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx/NAND: Add select_chip function to 4xx NDFC driverStefan Roese2008-08-30-0/+8
| | | | | | | This function is needed for the new NAND infrastructure. We only need a dummy implementation though for the NDFC. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: NAND configurationWolfgang Ocker2008-08-29-1/+5
| | | | | | | Made NAND bank configuration setting a config variable. Signed-off-by: Wolfgang Ocker <weo@reccoware.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: fix UIC external_interrupt hang on UIC0Victor Gallardo2008-08-29-2/+2
| | | | | | | | This patch fixes a UIC external_interrupt hang if critical or non-critical interrupt is set at the same time as a normal interrupt is set on UIC0. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Optimizations/Cleanups for IBM DDR2 Memory ControllerProdyut Hazarika2008-08-29-17/+56
| | | | | | | | | Removed Magic numbers from Initialization preload registers Tested with Kilauea, Glacier, Canyonlands and Katmai boards About 5-7% improvement seen for LMBench memtests Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fixTirumala R Marri2008-08-22-5/+5
| | | | | | | | | | | During recent PCI-E tests it has been found that current driverl level and de-emphasis values are not set correctly. After sweeping throgh all de-ephasis values, it was found that 0x130 is a right value. Where 0x13 is driver level and 0 is de-emphasis. Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patchStefan Roese2008-08-21-24/+13
| | | | | | | | | | | | | This patch fixes some minor issues introduced with the patch: ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika: - Rework memory-queue and PLB arbiter optimization code, that the local variable is not needed anymore. This removes one #ifdef. - Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead of XXX+ 0x01). This was not introduced by Prodyut, just a copy-paste problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,Prodyut Hazarika2008-08-21-5/+38
| | | | | | | | | | | | | | | PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* fdt: rework fdt_fixup_ethernet() to use env instead of bd_tKumar Gala2008-08-21-1/+1
| | | | | | | | | | Move to using the environment variables 'ethaddr', 'eth1addr', etc.. instead of bd->bi_enetaddr, bi_enet1addr, etc. This makes the code a bit more flexible to the number of ethernet interfaces. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'Makefile' of git://git.denx.de/u-boot-armWolfgang Denk2008-08-13-1/+1
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| * drivers/mtd/nand: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2008-08-13-1/+1
| | | | | | | | | | | | rename CFG_NAND_LEGACY to CONFIG_NAND_LEGACY Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-08-13-64/+48
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| * NAND: Update 4xx NDFC driver to match updated nand subsystemStefan Roese2008-08-12-42/+41
| | | | | | | | | | | | | | | | | | | | | | This patch changes the 4xx NAND driver ndfc.c to match the new infrastructure from the updated NAND subsystem. This NAND subsystem was recently synced again with the Linux 2.6.22 MTD/NAND subsystem. Tested successfully on AMCC Sequoia and Bamboo. Signed-off-by: Stefan Roese <sr@denx.de>
| * Fixing coding style issuesWilliam Juul2008-08-12-7/+7
| | | | | | | | | | | | | | | | | | - Fixing leading white spaces - Fixing indentation where 4 spaces are used instead of tab - Removing C++ comments (//), wherever I introduced them Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * Update MTD to that of Linux 2.6.22.1William Juul2008-08-12-36/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot changed in the Linux MTD code, since it was last ported from Linux to U-Boot. This patch takes U-Boot NAND support to the level of Linux 2.6.22.1 and will enable support for very large NAND devices (4KB pages) and ease the compatibility between U-Boot and Linux filesystems. This patch is tested on two custom boards with PPC and ARM processors running YAFFS in U-Boot and Linux using gcc-4.1.2 cross compilers. MAKEALL ppc/arm has some issues: * DOC/OneNand/nand_spl is not building (I have not tried porting these parts, and since I do not have any HW and I am not familiar with this code/HW I think its best left to someone else.) Except for the issues mentioned above, I have ported all drivers necessary to run MAKEALL ppc/arm without errors and warnings. Many drivers were trivial to port, but some were not so trivial. The following drivers must be examined carefully and maybe rewritten to some degree: cpu/ppc4xx/ndfc.c cpu/arm926ejs/davinci/nand.c board/delta/nand.c board/zylonite/nand.c Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Stig Olsen <stig.olsen@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * ppc4xx: Fix incorrect MODTx setup for some DIMM configurationsStefan Roese2008-07-18-12/+12
| | | | | | | | | | | | | | | | | | | | This patch fixes a problem with incorrect MODTx (On Die Termination) setup for a configuration with multiple DIMM's and multiple ranks. Without this change Katmai was unable to boot Linux with DDR2 frequency >= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux with DDR2 frequency = 640MHz and mem=4GB. Signed-off-by: Stefan Roese <sr@denx.de>
* | Fix merge problemsStefan Roese2008-08-06-12/+12
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 supportStefan Roese2008-07-18-36/+7
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: CPU PPC440x5 on Virtex5 FXRicardo Ribalda Delgado2008-07-18-153/+361
| | | | | | | | | | | | | | | | | | | | | | -This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-17-3/+3
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| * Code cleanup: fix old style assignment ambiguities like "=-" etc.Wolfgang Denk2008-07-14-3/+3
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-14-3/+3
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| * ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-13-2/+10
| | | | | | | | | | | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Fix include sequence in 4xx_pcie.cStefan Roese2008-07-11-3/+3
| | | | | | | | | | | | | | | | | | This patch now moves common.h to the top of the inlcude list. This is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that the phys_size_t/phys_addr_t are defined to the correct size in this driver. Signed-off-by: Stefan Roese <sr@denx.de>
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