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* ppc4xx: Remove CONFIG_CS8952_PHY defineStefan Roese2008-09-08-2/+0
| | | | | | | | Since this define is only used on one board that was never really in production, removing this compile time option doesn't hurt and makes the code more readable. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix compilation warning for PIP405Stefan Roese2008-09-08-6/+5
| | | | | | | | | | This patch fixes a compilation warning for the PIP405 board. It moves the #ifndef CONFIG_CS8952_PHY define a little so that the warning doesn't occur anymore. I am a little unsure if this #ifdef is at the correct place now or if it could be removed completely. This needs to get tested on the PIP405 board. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix compilation warning for canyonlands & glacierStefan Roese2008-09-08-7/+3
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add support for GPCS, SGMII and M88E1112 PHYVictor Gallardo2008-09-05-5/+195
| | | | | | | | This patch adds GPCS, SGMII and M88E1112 PHY support for the AMCC PPC460GT/EX processors. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Kilauea to use PPC4xx DDR autocalibration routinesAdam Graham2008-09-05-63/+98
| | | | | Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: IBM Memory Controller DDR autocalibration routinesAdam Graham2008-09-05-0/+1212
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Alternate SDRAM DDR autocalibration routine that can be generically used for any PPC4xx chips that have the IBM SDRAM Controller core allowing for support of more DIMM/memory chip vendors and gets the DDR autocalibration values which give the best read latency performance (SDRAM0_RDCC.[RDSS]). Two alternate SDRAM DDR autocalibration algoritm are provided in this patch, "Method_A" and "Method_B". DDR autocalibration Method_A scans the full range of possible PPC4xx SDRAM Controller DDR autocalibration values and takes a lot longer to run than Method_B. Method_B executes in the same amount of time as the currently existing DDR autocalibration routine, i.e. 1 second or so. Normally Method_B is used and it is set as the default method. The current U-Boot PPC4xx DDR autocalibration code calibrates the IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_RQDC.[RQFD] 2) SDRAM0_RFDC.[RFFD] This alternate PPC4xx DDR autocalibration code calibrates the following IBM SDRAM Controller registers.[bit-field]: 1) SDRAM0_WRDTR.[WDTR] 2) SDRAM0_CLKTR.[CKTR] 3) SDRAM0_RQDC.[RQFD] 4) SDRAM0_RFDC.[RFFD] and will also use the calibrated settings of the above four registers that produce the best "Read Sample Cycle Select" value in the SDRAM0_RDCC.[RDSS] register.[bit-field]. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx/NAND: Add select_chip function to 4xx NDFC driverStefan Roese2008-08-30-0/+8
| | | | | | | This function is needed for the new NAND infrastructure. We only need a dummy implementation though for the NDFC. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: NAND configurationWolfgang Ocker2008-08-29-1/+5
| | | | | | | Made NAND bank configuration setting a config variable. Signed-off-by: Wolfgang Ocker <weo@reccoware.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: fix UIC external_interrupt hang on UIC0Victor Gallardo2008-08-29-2/+2
| | | | | | | | This patch fixes a UIC external_interrupt hang if critical or non-critical interrupt is set at the same time as a normal interrupt is set on UIC0. Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Optimizations/Cleanups for IBM DDR2 Memory ControllerProdyut Hazarika2008-08-29-17/+56
| | | | | | | | | Removed Magic numbers from Initialization preload registers Tested with Kilauea, Glacier, Canyonlands and Katmai boards About 5-7% improvement seen for LMBench memtests Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fixTirumala R Marri2008-08-22-5/+5
| | | | | | | | | | | During recent PCI-E tests it has been found that current driverl level and de-emphasis values are not set correctly. After sweeping throgh all de-ephasis values, it was found that 0x130 is a right value. Where 0x13 is driver level and 0 is de-emphasis. Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patchStefan Roese2008-08-21-24/+13
| | | | | | | | | | | | | This patch fixes some minor issues introduced with the patch: ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika: - Rework memory-queue and PLB arbiter optimization code, that the local variable is not needed anymore. This removes one #ifdef. - Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead of XXX+ 0x01). This was not introduced by Prodyut, just a copy-paste problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,Prodyut Hazarika2008-08-21-5/+38
| | | | | | | | | | | | | | | PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* fdt: rework fdt_fixup_ethernet() to use env instead of bd_tKumar Gala2008-08-21-1/+1
| | | | | | | | | | Move to using the environment variables 'ethaddr', 'eth1addr', etc.. instead of bd->bi_enetaddr, bi_enet1addr, etc. This makes the code a bit more flexible to the number of ethernet interfaces. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'Makefile' of git://git.denx.de/u-boot-armWolfgang Denk2008-08-13-1/+1
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| * drivers/mtd/nand: Move conditional compilation to MakefileJean-Christophe PLAGNIOL-VILLARD2008-08-13-1/+1
| | | | | | | | | | | | rename CFG_NAND_LEGACY to CONFIG_NAND_LEGACY Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-08-13-64/+48
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| * NAND: Update 4xx NDFC driver to match updated nand subsystemStefan Roese2008-08-12-42/+41
| | | | | | | | | | | | | | | | | | | | | | This patch changes the 4xx NAND driver ndfc.c to match the new infrastructure from the updated NAND subsystem. This NAND subsystem was recently synced again with the Linux 2.6.22 MTD/NAND subsystem. Tested successfully on AMCC Sequoia and Bamboo. Signed-off-by: Stefan Roese <sr@denx.de>
| * Fixing coding style issuesWilliam Juul2008-08-12-7/+7
| | | | | | | | | | | | | | | | | | - Fixing leading white spaces - Fixing indentation where 4 spaces are used instead of tab - Removing C++ comments (//), wherever I introduced them Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * Update MTD to that of Linux 2.6.22.1William Juul2008-08-12-36/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | A lot changed in the Linux MTD code, since it was last ported from Linux to U-Boot. This patch takes U-Boot NAND support to the level of Linux 2.6.22.1 and will enable support for very large NAND devices (4KB pages) and ease the compatibility between U-Boot and Linux filesystems. This patch is tested on two custom boards with PPC and ARM processors running YAFFS in U-Boot and Linux using gcc-4.1.2 cross compilers. MAKEALL ppc/arm has some issues: * DOC/OneNand/nand_spl is not building (I have not tried porting these parts, and since I do not have any HW and I am not familiar with this code/HW I think its best left to someone else.) Except for the issues mentioned above, I have ported all drivers necessary to run MAKEALL ppc/arm without errors and warnings. Many drivers were trivial to port, but some were not so trivial. The following drivers must be examined carefully and maybe rewritten to some degree: cpu/ppc4xx/ndfc.c cpu/arm926ejs/davinci/nand.c board/delta/nand.c board/zylonite/nand.c Signed-off-by: William Juul <william.juul@tandberg.com> Signed-off-by: Stig Olsen <stig.olsen@tandberg.com> Signed-off-by: Scott Wood <scottwood@freescale.com>
| * ppc4xx: Fix incorrect MODTx setup for some DIMM configurationsStefan Roese2008-07-18-12/+12
| | | | | | | | | | | | | | | | | | | | This patch fixes a problem with incorrect MODTx (On Die Termination) setup for a configuration with multiple DIMM's and multiple ranks. Without this change Katmai was unable to boot Linux with DDR2 frequency >= 533MHz and mem>=3GB. With this patch Katmai successfully boots Linux with DDR2 frequency = 640MHz and mem=4GB. Signed-off-by: Stefan Roese <sr@denx.de>
* | Fix merge problemsStefan Roese2008-08-06-12/+12
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Minor coding style cleanup of Xilinx Virtex5 ml507 supportStefan Roese2008-07-18-36/+7
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: CPU PPC440x5 on Virtex5 FXRicardo Ribalda Delgado2008-07-18-153/+361
| | | | | | | | | | | | | | | | | | | | | | -This patchs gives support for the embbedded ppc440 on the Virtex5 FPGAs -interrupts.c divided in uic.c and interrupts.c -xilinx_irq.c for xilinx interrupt controller -Include modifications propossed by Stefan Roese Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Acked-by: Stefan Roese <sr@denx.de>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-17-3/+3
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| * Code cleanup: fix old style assignment ambiguities like "=-" etc.Wolfgang Denk2008-07-14-3/+3
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge branch 'master' of /home/stefan/git/u-boot/u-boot into nextStefan Roese2008-07-14-3/+3
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| * ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-13-2/+10
| | | | | | | | | | | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Fix include sequence in 4xx_pcie.cStefan Roese2008-07-11-3/+3
| | | | | | | | | | | | | | | | | | This patch now moves common.h to the top of the inlcude list. This is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that the phys_size_t/phys_addr_t are defined to the correct size in this driver. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix compile warning in 44x_spd_ddr2.cStefan Roese2008-07-11-2/+2
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Rework 440GX UIC handlingStefan Roese2008-07-11-85/+36
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-328/+157
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This 2nd patch now removes all UIC mask bit definition. They should be generated from the vectors by using the UIC_MASK() macro from now on. This way only the vectors need to get defined for new PPC's. Also only the really used interrupt vectors are now defined. This makes definitions for new PPC versions easier and less error prone. Another part of this patch is that the 4xx emac driver got a little cleanup, since now the usage of the interrupts is clearer. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Consolidate PPC4xx UIC definesStefan Roese2008-07-11-5/+2
| | | | | | | | | | | | | | | | | | This patch is the first step to consolidate the UIC related defines in the 4xx headers. Move header from asm-ppc/ppc4xx-intvec.h to asm-ppc/ppc4xx-uic.h as it will hold all UIC related defines in the next steps. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Remove redundant ft_board_setup() functions from some 4xx boardsStefan Roese2008-07-11-2/+10
| | | | | | | | | | | | | | | | | | This patch removes some ft_board_setup() functions from some 4xx boards. This can be done since we now have a default weak implementation for this in cpu/ppc4xx/fdt.c. Only board in need for a different/custom implementation like canyonlands need their own version. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix merge problems in 44x_spd_ddr2.cStefan Roese2008-07-11-16/+19
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add MII mode support to the EMAC RGMII BridgeGrant Erickson2008-07-11-11/+69
| | | | | | | | | | | | | | | | | | This patch adds support for placing the RGMII bridge on the PPC405EX(r) into MII/GMII mode and allows a board-specific configuration to specify the bridge mode at compile-time. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add Mnemonics for AMCC/IBM DDR2 SDRAM ControllerGrant Erickson2008-07-11-165/+97
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch completes the preprocessor mneomics for the IBM DDR2 SDRAM controller registers (MODT and INITPLR) used by the PowerPC405EX(r). The MMODE and MEMODE registers are unified with their peer values used for the INITPLR MR and EMR registers, respectively. Finally, a spelling typo is correct (MANUEL to MANUAL). With these mnemonics in place, the CFG_SDRAM0_* magic numbers for Kilauea are replaced by equivalent mnemonics to make it easier to compare and contrast other 405EX(r)-based boards (e.g. during board bring-up). Finally, unified the SDRAM controller register dump routine such that it can be used across all processor variants that utilize the IBM DDR2 SDRAM controller core. It produces output of the form: PPC4xx IBM DDR2 Register Dump: ... SDRAM_MB0CF[40] = 0x00006701 ... which is '<mnemonic>[<DCR #>] = <value>'. The DCR number is included since it is not uncommon that the DCR values in header files get mixed up and it helps to validate, at a glance, they match what is printed in the user manual. Tested on: AMCC Kilauea/Haleakala: - NFS Linux Boot: PASSED - NAND Linux Boot: PASSED Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add initial 460SX defines for the cpu/ppc4xx directory.Feng Kan2008-07-11-4/+54
|/ | | | | Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix printf format warnings now visible with the updated format checkStefan Roese2008-07-10-25/+25
| | | | | | | | | This patch fixes ppc4xx related printf format warning. Those warnings are now visible since patch dc4b0b38d4aadf08826f6c31270f1eecd27964fd [Fix printf errors.] by Andrew Klossner has been applied. Thanks, this is really helpful. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable support for > 2GB SDRAM on AMCC KatmaiStefan Roese2008-07-10-11/+45
| | | | | | | | | | | | | Newer PPC's like 440SPe, 460EX/GT can be equipped with more than 2GB of SDRAM. To support such configurations, we "only" map the first 2GB via the TLB's. We need some free virtual address space for the remaining peripherals like, SoC devices, FLASH etc. Note that ECC is currently not supported on configurations with more than 2GB SDRAM. This is because we only map the first 2GB on such systems, and therefore the ECC parity byte of the remaining area can't be written. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of /home/stefan/git/u-boot/u-bootStefan Roese2008-07-07-1/+1
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| * ppc4xx: Rename CONFIG_XILINX_ML300 to CONFIG_XILINX_405Michal Simek2008-07-06-1/+1
| | | | | | | | | | | | | | | | This change helps with better handling with others Xilinx based platform. Signed-off-by: Michal Simek <monstr@monstr.eu> Acked-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix 460EX/GT PCIe port initializationStefan Roese2008-07-01-7/+5
|/ | | | | | | | This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 460EX errata with CPU lockup upon high AHB trafficStefan Roese2008-06-30-2/+18
| | | | | | | | | | | | | | | This patch implements a fix provided by AMCC so that the lockup upon simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur anymore: Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA. This errata is not officially available yet. I'll update the comment to add the errata number later. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem in gpio_config()Stefan Roese2008-06-23-2/+2
| | | | | | | As pointed out by Guennadi Liakhovetski (thanks), pin2 is already shifted left by one. So the additional shift is bogus. Signed-off-by: Stefan Roese <sr@denx.de>
* Change initdram() return type to phys_size_tBecky Bruce2008-06-12-5/+5
| | | | | | | | | | | | | | | | | | | This patch changes the return type of initdram() from long int to phys_size_t. This is required for a couple of reasons: long int limits the amount of dram to 2GB, and u-boot in general is moving over to phys_size_t to represent the size of physical memory. phys_size_t is defined as an unsigned long on almost all current platforms. This patch *only* changes the return type of the initdram function (in include/common.h, as well as in each board's implementation of initdram). It does not actually modify the code inside the function on any of the platforms; platforms which wish to support more than 2GB of DRAM will need to modify their initdram() function code. Build tested with MAKEALL for ppc, arm, mips, mips-el. Booted on powerpc MPC8641HPCN. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* ppc4xx: Fix misspelled CONFIG_440SPE/440EPX/GRX config optionsStefan Roese2008-06-06-5/+5
| | | | | | | | We use upper case letters for the AMCC processor defines (like CONFIG_440SPE) in U-Boot. So the 440SPe is labeled CONFIG_440SPE and not CONFIG_440SPe. This patch fixes the last misspelled config options. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove superfluous dram_init() call or replace it by initdram()Stefan Roese2008-06-03-8/+8
| | | | | | | | | | | | | | | | | | | | | | | | | | | Historically the 405 U-Boot port had a dram_init() call in early init stage. This function was still called from start.S and most of the time coded in assembler. This is not needed anymore (since a long time) and boards should implement the common initdram() function in C instead. This patch now removed the dram_init() call from start.S and removes the empty implementations that are scattered through most of the 405 board ports. Some older board ports really implement this dram_init() though. These are: csb272 csb472 ERIC EXBITGEN W7OLMC W7OLMG I changed those boards to call this assembler dram_init() function now from their board specific initdram() instead. This *should* work, but please test again on those platforms. And it is perhaps a good idea that those boards use some common 405 SDRAM initialization code from cpu/ppc4xx at some time. So further patches welcome here. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Use new 4xx SDRAM controller enable defines in common ECC codeStefan Roese2008-06-03-2/+3
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix common ECC generation code for 440GP style platformsStefan Roese2008-06-03-7/+34
| | | | | | | | | | | | This patch makes the common 4xx ECC code really usable on 440GP style platforms. Since the IBM DDR controller used on 440GP/GX/EP/GR is not register compatible to the IBM DDR/2 controller used on 405EX/440SP/SPe/460EX/GT we need to make some processor dependant defines used later on by the driver. Signed-off-by: Stefan Roese <sr@denx.de>
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