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* ppc4xx: Set default PCI device ID for 405EP boardsMatthias Fuchs2009-07-10-2/+9
| | | | | | | | | | | | | Current code only sets the PCI vendor id to 0x1014 and leaved device id to 0x0000. Ths patch .... a) uses the correct PCI_VENDOR_ID_IBM macro for this b) sets the default device ID as stated in the UM to 0x0156 by using PCI_DEVICE_ID_IBM_405GP for this. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()Matthias Fuchs2009-07-10-5/+14
| | | | | | | | | | | | | | | | | | | | This patch moves some basic PCI initialisation from the 4xx cpu_init_f() to cpu/ppc4xx/4xx_pci.c. The original cpu_init_f() function enabled the 405EP's internal arbiter in all situations. Also the HCE bit in cpc0_pci is always set. The first is not really wanted for PCI adapter designs and the latter is a general bug for PCI adapter U-Boots. Because it enables PCI configuration by the system CPU even when the PCI configuration has not been setup by the 405EP. The one and only correct place is in pci_405gp_init() (see "Set HCE bit" comment). So for compatibility reasons the arbiter is still enabled in any case, but from weak pci_pre_init() so that it can be replaced by board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make pll_write globalMatthias Fuchs2009-07-08-0/+1
| | | | | | | | | | | | | | This patch makes pll_write on PPC405EP boards global and callable from C code. pll_write can be used to dynamically modify the PLB:PCI divider as it is required for 33/66 MHz pci adapters based on the 405EP. board_early_init_f() is a good place to do that (check M66EN signal and call pll_write() when it is required). Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove compilation warning "pci_async_enabled defined but not used"Stefan Roese2009-07-08-0/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Implement is_pci_host() for 405 CPUsMatthias Fuchs2009-07-08-3/+16
| | | | | | | | | | | | | | | | | | | This patch implements the is_pci_host() function in a similiar way as it is used on 440 targets. The former path with CONFIG_PCI_HOST == PCI_HOST_AUTO does not build on 405EP targets because checking the PCI arbiter is different. So putting the fixed code into a separate function makes the code more readable. Also using is_pci_host() on 405 brings 405 and 440 PCI code a little bit closer. In preparation for an upcoming 405EP based PMC module I made this function weak so that it can be overwritten from board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fixed PPC4xx debug compilation error in uic.cAlessio Centazzo2009-07-08-1/+1
| | | | | | | | | | This patch fixes a debug compilation error for PPC4xx platforms, all other architectures are not affected by this change. The 'handler' pointer was undefined. The fix is exercised and has effect only if DEBUG is defined. Signed-off-by: Alessio Centazzo acpatin@yahoo.com Signed-off-by: Stefan Roese <sr@denx.de>
* 4xx: Fix compilation warnings and MQ registers dump in SPD DDR2 codeFelix Radensky2009-07-08-17/+25
| | | | | | | | | | This patch fixes printf format string compilation warnings in several debug statements. It also fixes the dump of DDR controller MQ registers found on some 44x and 46x platforms. The current register dump code uses incorrect DCRs to access these registers. Signed-off-by: Felix Radensky <felix@embedded-sol.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove PCI async bootup message if PCI is not usedStefan Roese2009-06-12-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Sequoia RAM-booting targetStefan Roese2009-06-12-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
* i2c: Create common default i2c_[set|get]_bus_speed() functionsPeter Tyser2009-06-12-14/+0
| | | | | | | | | | | | | New default, weak i2c_get_bus_speed() and i2c_set_bus_speed() functions replace a number of architecture-specific implementations. Also, providing default functions will allow all boards to enable CONFIG_I2C_CMD_TREE. This was previously not possible since the tree-form of the i2c command provides the ability to display and modify the i2c bus speed which requires i2c_[set|get]_bus_speed() to be present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* i2c.h: Provide a default CONFIG_SYS_I2C_SLAVE valuePeter Tyser2009-06-12-8/+0
| | | | | | | | Many boards/controllers/drivers don't support an I2C slave interface, however CONFIG_SYS_I2C_SLAVE is used in common code so provide a default Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Fix problem with ECC ordering for PPC4xx NDFC platformsStefan Roese2009-05-23-2/+2
| | | | | | | | | | | | | This patch now uses the correct ECC byte order (Smart Media - SMC) to be used on the 4xx NAND FLASH driver. Without this patch we have incompatible ECC byte ordering to the Linux kernel NDFC driver. Please note that we also have to enable CONFIG_MTD_NAND_ECC_SMC in drivers/mtd/nand/nand_ecc.c for correct operation. This is done with a seperate patch. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* ppc4xx: Move definition for PPC4xx NAND FLASH controller to headerStefan Roese2009-05-23-6/+3
| | | | | | | | | This patch moves the definition for the PPC4xx NAND FLASH controller (NDFC) CONFIG_NAND_NDFC into include/ppc4xx.h. This is needed for the upcoming fix for the ECC byte ordering of the NDFC driver. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* Fix e-mail address of Gary Jennejohn.Detlev Zundel2009-05-15-1/+1
| | | | Signed-off-by: Detlev Zundel <dzu@denx.de>
* Replace __attribute references with __attribute__Peter Tyser2009-04-28-4/+4
| | | | | | | | __attribute__ follows gcc's documented syntax and is generally more common than __attribute. This change is only asthetic and should not affect functionality. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Add "booting from NAND" to 4xx NAND-booting targetsStefan Roese2009-04-16-1/+5
| | | | | | | | This additional text in the bootup log helps to see if the board is configured for NAND-booting. Especially helpful for boards that can boot from NOR and NAND (e.g. most of the AMCC eval boards). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Don't write the MAC address into the internal SoC registersStefan Roese2009-03-20-28/+1
| | | | | | | Remove this code. It's not needed. The 4xx EMAC driver stores the MAC addresses into the SoC registers instead. Signed-off-by: Stefan Roese <sr@denx.de>
* cpu/: get mac address from environmentMike Frysinger2009-03-20-6/+8
| | | | | | | | | | | | | | | | | | | The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. The cpus that get converted here: at91rm9200 mpc512x mpc5xxx mpc8260 mpc8xx ppc4xx Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com> CC: John Rigby <jrigby@freescale.com> CC: Stefan Roese <sr@denx.de>
* ppc4xx: Fix bug in PCI outbound map configuration for canyonlandsAnatolij Gustschin2009-03-20-2/+4
| | | | | | | | | | | | | | PCI outbound address map configuration doesn't match the PCI memory address range covered by appropriate TLB entry configuration for canyonlands causing machine check exceptions while accessing PCI memory regions. This patch provides a fix for this issue. Kazuaki Ichinohe observed and reported this issue while testing display output with PCI ATI video card on canyonlands. Signed-off-by: Anatolij Gustschin <agust@denx.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: PCIe: Change 16GB inbound memory to 4GBStefan Roese2009-02-18-2/+2
| | | | | | | This patch fixes a problem recently seen on some 4xx platforms. For example on Kilauea PCIe slot #0. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix initialization of the SDRAM_CODT registerCarolyn Smith2009-02-12-5/+2
| | | | | | | | | This fixes the initialization of the SDRAM_CODT register in the ppc4xx DDR2 initialization code. It also removes use of the SDRAM_CODT_FEEDBACK_RCV_SINGLE_END and SDRAM_CODT_FEEDBACK_DRV_SINGLE_END #define's since they are reserved bits. Signed-off-by: Carolyn Smith <carolyn.smith@tektronix.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Autocalibration can set RDCC to over aggressive value.Adam Graham2009-02-12-29/+45
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The criteria of the AMCC SDRAM Controller DDR autocalibration U-Boot code is to pick the largest passing write/read/compare window that also has the smallest SDRAM_RDCC.[RDSS] Read Sample Cycle Select value. On some Kilauea boards the DDR autocalibration algorithm can find a large passing write/read/compare window with a small SDRAM_RDCC.[RDSS] aggressive value of Read Sample Cycle Select value "T1 Sample". This SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" proves to be to aggressive when later on U-Boot relocates into DDR memory and executes. The memory traces on the Kilauea board are short so on some Kilauea boards the SDRAM_RDCC.[RDSS] Read Sample Cycle Select value of "T1 Sample" shows up as a potentially valid value for the DDR autocalibratiion algorithm. The fix is to define a weak default function which provides the minimum SDRAM_RDCC.[RDSS] Read Sample Cycle Select value to accept for DDR autocalibration. The default will be the "T2 Sample" value. A board developer who has a well defined board and chooses to be more aggressive can always provide their own board specific string function with the more aggressive "T1 Sample" value or stick with the default minimum SDRAM_RDCC.[RDSS] value of "T2". Also put in a autocalibration loop fix for case where current write/read/compare passing window size is the same as a prior window size, then in this case choose the write/read/compare result that has the associated smallest RDCC T-Sample value. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc: Move CONFIG_MAX_MEM_MAPPED to common config.hKumar Gala2009-02-10-3/+0
| | | | | | | | Moved CONFIG_MAX_MEM_MAPPED to the asm/config.h so its kept consistent between the two current users (lib_ppc/board.c, 44x SPD DDR2). Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Stefan Roese <sr@denx.de>
* pci: Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY for clarityKumar Gala2009-02-07-2/+2
| | | | | | | | | | The PCI_REGION_MEMORY and PCI_REGION_MEM are a bit to similar and can be confusing when reading the code. Rename PCI_REGION_MEMORY to PCI_REGION_SYS_MEMORY to clarify its used for system memory mapping purposes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc4xx: Make PCIE support selectableDirk Eibach2009-02-06-3/+4
| | | | | | | | | On some platforms PCIE support is not required, but would be included because the cpu supports it. To reduce fooprint it is now configurable via CONFIG_PCI_DISABLE_PCIE. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Only fixup opb attached UARTsMatthias Fuchs2009-02-06-2/+22
| | | | | | | | | This patch updates the fdt UART clock fixup code to only touch CPU internal UARTs on 4xx systems. Only these UARTs are definitely clocked by gd->uart_clk. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Standardize command usage messages with cmd_usage()Peter Tyser2009-01-28-2/+2
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Improve DDR autodetectDirk Eibach2009-01-26-5/+50
| | | | | | | | | Added support for a second memory bank to DDR autodetection for 440 platforms. Made hardcoded values configurable. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanup, update CHANGELOG.Wolfgang Denk2008-12-16-2/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* i2c: merge all i2c_reg_read() and i2c_reg_write() into inline functionsTimur Tabi2008-12-15-20/+0
| | | | | | | | | | All implementations of the functions i2c_reg_read() and i2c_reg_write() are identical. We can save space and simplify the code by converting these functions into inlines and putting them in i2c.h. Signed-off-by: Timur Tabi <timur@freescale.com> Acked-By: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Section name should be ".data", not "data"Trent Piepho2008-12-09-4/+3
| | | | | Signed-off-by: Trent Piepho <tpiepho@freescale.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-1/+2
| | | | | | | Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initializationDave Mitchell2008-11-21-7/+20
| | | | | | | | | | | | | | | | | | Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRsDave Mitchell2008-11-21-20/+21
| | | | | | | | | | | Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header. Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Clear all potentially pending exceptions in MCSRStefan Roese2008-11-20-0/+4
| | | | | | | | This is needed on Canyonlands which still has an exception pending while running relocate_code(). This leads to a failure after trap_init() is moved to the top of board_init_r(). Signed-off-by: Stefan Roese <sr@denx.de>
* Moved initialization of PPC4xx EMAC to cpu_eth_init()Ben Warren2008-11-09-0/+14
| | | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* Moved PPC4xx EMAC driver to drivers/netBen Warren2008-11-09-2128/+0
| | | | | | | Also changed path in all linker scripts that reference this driver Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* Changed PPC4xx EMAC driver to require CONFIG_PPC4xx_EMACBen Warren2008-11-09-9/+1
| | | | | | | All in-tree IBM/AMCC PPC4xx boards using the EMAC get this new CONFIG Signed-off-by: Ben Warren <biggerbadderben@gmail.com> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx: Generic architecture for xilinx ppc405(v3)Ricardo Ribalda Delgado2008-10-24-1/+2
| | | | | | | | | | | | | | | | | As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://git.denx.de/u-boot-ppc4xxWolfgang Denk2008-10-21-36/+99
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| * ppc4xx: Correctly setup ranges property in ebc nodeStefan Roese2008-10-21-17/+28
| | | | | | | | | | | | | | | | Previously only the NOR flash mapping was written into the ranges property of the ebc node. This patch now writes all enabled chip select areas into the ranges property. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add routine to retrieve CPU numberAdam Graham2008-10-21-1/+18
| | | | | | | | | | | | | | | | | | | | | | | | Provide a weak defined routine to retrieve the CPU number for reference boards that have multiple CPU's. Default behavior is the existing single CPU print output. Reference boards with multiple CPU's need to provide a board specific routine. See board/amcc/arches/arches.c for an example. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add static support for 44x IBM SDRAM ControllerAdam Graham2008-10-21-18/+53
| | | | | | | | | | | | | | | | | | | | This patch add the capability to configure a PPC440 based IBM SDRAM Controller with static, compiled-in, values. PPC440 memory subsystem includes a Memory Queue core. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* | Cleanup: fix "MHz" spellingWolfgang Denk2008-10-21-3/+3
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* | Merge git://git.denx.de/u-boot into x1Markus Klotzbuecher2008-10-21-521/+544
|\ \ | |/ | | | | | | | | Conflicts: drivers/usb/usb_ohci.c
| * Merge 'next' branchWolfgang Denk2008-10-18-517/+517
| |\ | | | | | | | | | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| | * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-517/+517
| | | | | | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
| * | ppc4xx: PPC44x MQ initializationYuri Tikhonov2008-10-17-4/+6
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Set the MQ Read Passing & MCIF Cycle limits to the recommended by AMCC values. This fixes the occasional 440SPe hard locking issues when the 440SPe's dedicated DMA engines are used (e.g. by the h/w accelerated RAID driver). Previously the appropriate initialization had been made in Linux, by the ppc440spe ADMA driver, which is wrong because modifying the MQ configuration registers after normal operation has begun is not supported and could have unpredictable results. Comment from Stefan: This patch doesn't change the resulting value of the MQ registers. It explicitly sets/clears all bits to the desired state which better documents the resulting register value instead of relying on pre-set default values. Signed-off-by: Yuri Tikhonov <yur@emcraft.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Reset and relock memory DLL after SDRAM_CLKTR changeAdam Graham2008-10-08-0/+21
| | | | | | | | | | | | | | | | | | | | | | | | After changing SDRAM_CLKTR phase value rerun the memory preload initialization sequence (INITPLR) to reset and relock the memory DLL. Changing the SDRAM_CLKTR memory clock phase coarse timing adjustment effects the phase relationship of the internal, to the PPC chip, and external, to the PPC chip, versions of MEMCLK_OUT. Signed-off-by: Adam Graham <agraham@amcc.com> Signed-off-by: Victor Gallardo <vgallardo@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * Revert "ppc4xx: Fix DDR2 auto calibration on Kilauea 600MHz (200MHz PLB)"Stefan Roese2008-09-22-0/+5
| | | | | | | | | | | | This reverts commit 3eec160a3a405b29ce9c06920f6427b9047dd8a8. Signed-off-by: Stefan Roese <sr@denx.de>
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