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* Merge git://www.denx.de/git/u-boot into 2007_05_15-testingMarkus Klotzbuecher2007-05-29-5/+5
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| * ppc4xx: Add 405 support to 4xx NAND driver ndfc.cStefan Roese2007-05-22-4/+4
| | | | | | | | | | | | | | This patch adds support for 405 PPC's to the 4xx NAND driver ndfc.c. This is in preparation for the new AMCC 405EZ. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Fix problem in 405EZ OCM initializationStefan Roese2007-05-21-1/+1
| | | | | | | | | | | | | | As spotted by Bruce Adler this patch fixes an initialization problem for the 405EZ OCM. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with git://www.denx.de/git/u-boot.gitMarkus Klotzbuecher2007-05-07-9/+21
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| * Coding stylke cleanup; update CHANGELOG.Wolfgang Denk2007-05-05-2/+2
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Merge with git://www.denx.de/git/u-boot.gitStefan Roese2007-04-29-28/+28
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| * | ppc4xx: setup 440EPx/GRx ZMII/RGMII bridge depending on PFC register content.Matthias Fuchs2007-04-24-9/+21
| | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | Merge with git://www.denx.de/git/u-boot.gitMarkus Klotzbuecher2007-04-23-255/+408
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| * | Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xxWolfgang Denk2007-04-18-28/+28
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| | * Merge with /home/git/u-bootWolfgang Denk2007-03-08-26/+40
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| | * \ Merge with /home/git/u-bootWolfgang Denk2007-03-08-4/+27
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| | * | | Some code cleanup.Wolfgang Denk2007-03-04-41/+41
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| * | | | ppc4xx: Add output for bootrom location to 405EZ portsStefan Roese2007-04-18-4/+26
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Now 405EZ ports also show upon bootup from which boot device they are configured to boot: U-Boot 1.2.0-gd3832e8f-dirty (Apr 18 2007 - 07:47:05) CPU: AMCC PowerPC 405EZ Rev. A at 199.999 MHz (PLB=133, OPB=66, EBC=66 MHz) Bootstrap Option E - Boot ROM Location EBC (32 bits) 16 kB I-Cache 16 kB D-Cache Board: Acadia - AMCC PPC405EZ Evaluation Board Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Fix i2c divisor calcularion for PPC4xxJeffrey Mann2007-04-12-3/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes changes the i2c_init(...) function to use the function get_OPB_freq() rather than calculating the OPB speed by sysInfo.freqPLB/sysInfo.pllOpbDiv. The get_OPB_freq() function is specific per processor. The prior method was not and so was calculating the wrong speed for some PPC4xx processors. Signed-off-by: Jeffrey Mann <mannj@embeddedplanet.com> Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-03-31-19/+49
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Additional RAM information is now printed upon powerup, like DDR2 frequency and CAS latency. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-03-31-48/+81
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Fix a bug in the auto calibration routine. This driver now runs more reliable with the tested modules. It's also tested with 167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai. Signed-off-by: Stefan Roese <sr@denx.de>
| * | | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-156/+226
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| | * | | | [PATCH] Add 4xx GPIO functionsStefan Roese2007-03-24-114/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | | [PATCH] Clean up 40EZ/Acadia supportStefan Roese2007-03-24-42/+223
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up all the open issue of the preliminary Acadia support. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | Merge with git://www.denx.de/git/u-boot.git#testing-USBMarkus Klotzbuecher2007-03-23-2/+2
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| * | | | | Merge with /home/mk/git/u-boot-generic_ohci#generic_ohciWolfgang Denk2006-11-27-3/+2
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| | * | | | | Modified the mpc5xxx and the ppc4xx cpu to use the generic OHCI driverMarkus Klotzbuecher2006-11-27-1/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | and adapted board configs TQM5200 and yosemite accordingly. This commit also makes the maximum number of root hub ports configurable (CFG_USB_OHCI_MAX_ROOT_PORTS).
* | | | | | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-21-37/+323
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| * | | | | | [PATCH] Add AMCC PPC405EZ supportStefan Roese2007-03-21-37/+323
| | |_|/ / / | |/| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | | [PATCH] 4xx: allow CONFIG_I2C_CMD_TREE without CONFIG_I2C_MULTI_BUSMatthias Fuchs2007-03-08-1/+1
| |_|_|_|/ |/| | | | | | | | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-26/+40
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| * | | | Merge with /home/stefan/git/u-boot/yucca-ddr2Stefan Roese2007-03-08-26/+40
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| | * | | | [PATCH] Update AMCC Luan 440SP eval board supportStefan Roese2007-03-08-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
| | * | | | ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SPStefan Roese2007-03-08-25/+39
| | |/ / / | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-07-4/+27
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| * | | | [PATCH] Fix AMCC 44x SPD SDRAM init code to support 2 DIMM'sStefan Roese2007-03-07-4/+27
| |/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem that occurs when 2 DIMM's are used. This problem was first spotted and fixed by Gerald Jackson <gerald.jackson@reaonixsecurity.com> but this patch fixes the problem in a little more clever way. This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. As this feature is new to the "old" 44x SPD DDR driver, it has to be enabled via the CONFIG_PROG_SDRAM_TLB define. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Restructure POST directory to support of other CPUs, boards, etc.Wolfgang Denk2007-03-06-35/+35
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* | | Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-03-01-24/+24
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| * | | Minor code cleanup.Wolfgang Denk2007-02-27-27/+27
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* | | | [PATCH] Update AMCC Katmai 440SPe eval board supportStefan Roese2007-03-01-99/+323
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] Add support for the AMCC Katmai (440SPe) eval boardStefan Roese2007-02-20-8/+64
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-0/+2943
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Split 4xx SPD SDRAM init routines into 2 filesStefan Roese2007-02-20-413/+478
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Since the existing 4xx SPD SDRAM initialization routines for the 405 SDRAM controller and the 440 DDR controller don't have much in common this patch splits both drivers into different files. This is in preparation for the 440 DDR2 controller support (440SP/e). Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] PPC4xx: Add support for multiple I2C bussesStefan Roese2007-02-20-213/+245
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for multiple I2C busses on the PPC4xx platforms. Define CONFIG_I2C_MULTI_BUS in the board config file to make use of this feature. It also merges the 405 and 440 i2c header files into one common file 4xx_i2c.h. Also the 4xx i2c reset procedure is reworked since I experienced some problems with the first access on the 440SPe Katmai board. Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] Correctly display PCI arbiter en-/disabled on some 4xx boardsStefan Roese2007-02-02-6/+10
| | | | | | | | | | | | | | | | | | | | | | | | Previously the strapping DCR/SDR was read to determine if the internal PCI arbiter is enabled or not. This strapping bit can be overridden, so now the current status is read from the correct DCR/SDR register. Signed-off-by: Stefan Roese <sr@denx.de>
* | | [PATCH] Update 440EPx/440GRx cpu detectionStefan Roese2007-01-31-4/+8
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge with /home/hs/SC3/u-boot-devWolfgang Denk2007-01-19-6/+3
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| * | | [PATCH] Fix: Compilerwarnings for SC3 board.Heiko Schocher2007-01-18-6/+3
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The EBC Configuration Register is now by CFG_EBC_CFG definable Added JFFS2 support for the SC3 board. Signed-off-by: Heiko Schocher <hs@denx.de>
* | | | [PATCH] Add support for AMCC Taishan PPC440GX eval boardStefan Roese2007-01-18-76/+104
|/ / / | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | Merge with /home/hs/SC3/u-bootWolfgang Denk2007-01-15-3/+12
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| * | | Added support for the SOLIDCARD III board from EurodesignHeiko Schocher2007-01-11-2/+7
| | | | | | | | | | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | | | [PATCH] Fix 440SPe rev B detection from previous patchStefan Roese2007-01-15-1/+1
| | | | | | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | | | [PATCH] Update 440SP(e) cpu revisionsStefan Roese2007-01-13-4/+24
| | | | | | | | | | | | | | | | | | | | | | | | Also display enabled/disabled RAID 6 support for 440SP/440SPe PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | [PATCH] 44x: Fix problem with DDR controller setup (refresh rate)Stefan Roese2007-01-06-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch fixes a problem with an incorrect setup for the refresh timer of the 44x DDR controller in the file cpu/ppc4xx/sdram.c Signed-off-by: Stefan Roese <sr@denx.de>
* | | | [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-3/+0
|/ / / | | | | | | | | | | | | | | | | | | | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
generated by cgit v1.1 at 2024-11-25 16:05:44 +0000