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* ppc4xx: EMAC: Fix 405EZ fifo size setup in EMAC_MR1Stefan Roese2008-03-02-2/+3
| | | | | | | | | The 405EZ only supports 512 bytes of rx-/tx-fifo EMAC sizes. But currently 4k/2k is configured. This patch fixes this issue. Thanks to Thomas Kindler <tkindler@lenord.de> for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem in 4xx_enet.c driverAnatolij Gustschin2008-03-02-1/+9
| | | | | | | | | | U-Boot crashes in the net loop if CONFIG_4xx_DCACHE is enabled. To reproduce the problem ensure that 'ethrotate' environment variable isn't set to "no" and then run "tftp 200000 not_existent_file". This patch tries to fix the issue. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* cpu/ppc4xx/config.mk: Make a needlessly deffered expansion immediate.Shinya Kuribayashi2008-02-23-1/+1
| | | | | | This will reduce the build time. Signed-off-by: Shinya Kuribayashi <skuribay@ruby.dti.ne.jp>
* Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-02-15-5/+9
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| * ppc4xx: Add CONFIG_4xx_DCACHE compile switch to Denali-core SPD codeLarry Johnson2008-02-14-3/+3
| | | | | | | | Signed-off-by: Larry Johnson <lrj@acm.org>
| * ppc4xx: Fix ndfc HW ECC byte orderStefan Roese2008-02-04-2/+2
| | | | | | | | | | | | | | | | | | | | | | The current ndfc HW ECC implementation swaps the first two ECC bytes. But the 4xx NDFC already uses the SMC (Smart Media Card) ECC ordering, so this swapping in the HW ECC driver is bogus. This patch fixes this problem and now really uses the SMC ECC byte order. Thanks to Sean MacLennan for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Fix problem with init-ram bigger than 4k on 440 platformsStefan Roese2008-02-04-0/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | PPC: Use r2 instead of r29 as global data pointerWolfgang Denk2008-02-14-1/+1
| | | | | | | | | | | | | | | | | | | | | | | | R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc will refuse to use load/store multiple insns; instead, it issues a list of simple load/store instructions upon function entry and exit, resulting in bigger code size, which in turn makes the build for a few boards fail. Use r2 instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-33/+0
|/ | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* ppc4xx: Remove compiler warning in cpu/ppc4xx/44x_spd_ddr2.cStefan Roese2008-01-15-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix dflush() to restore DVLIM registerLarry Johnson2008-01-10-0/+2
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* fix comments with new drivers organizationMarcel Ziswiler2008-01-09-1/+1
| | | | Signed-off-by: Marcel Ziswiler <marcel@ziswiler.com>
* Merge branch 'lwmon5-no-ocm'Stefan Roese2008-01-09-1/+65
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| * ppc4xx: Add CFG_POST_ALT_WORD_ADDR to support non OCM POST WORD storageStefan Roese2008-01-09-1/+13
| | | | | | | | | | | | | | | | | | | | The privious 4xx POST implementation only supported storing the POST WORD in OCM. Since we need to reserve the OCM on LWMON5 for the logbuffer we need to store the POST WORD in some other non volatile location. This patch adds CFG_POST_ALT_WORD_ADDR to specify an address for such a location. Signed-off-by: Stefan Roese <sr@denx.de>
| * ppc4xx: Add 44x cache locking to better support init-ram in d-cacheStefan Roese2008-01-09-0/+52
| | | | | | | | | | | | | | | | | | | | | | This patch adds support for locking the init-ram/stack in d-cache, so that other regions may use d-cache as well Note, that this current implementation locks exactly 4k of d-cache, so please make sure that you don't define a bigger init-ram area. Take a look at the lwmon5 440EPx implementation as a reference. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Move cpu/ppc4xx/vecnum.h into include pathMatthias Fuchs2008-01-09-408/+5
| | | | | | | | | | | | | | This patch allows the use of 4xx interrupt vector number defines in board specific code outside cpu/ppc4xx. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | ppc4xx: Fix UIC2 vector number baseMatthias Fuchs2008-01-09-16/+16
| | | | | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* | ppc4xx: Return 0 on success in 4xx ethernet driverStefan Roese2008-01-08-2/+3
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Remove weak binding from common Denali data-eye search codeLarry Johnson2008-01-05-7/+0
| | | | | | | | | | | | | | | | Now that there are no board-specific versions of "denali_core_search_data_eye()", the weak binding on the common version can be removed. Signed-off-by: Larry Johnson <lrj@acm.org>
* | Merge branch 'katmai-ddr-gda'Stefan Roese2008-01-05-59/+37
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| * | ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from 44x_spd_ddr2.cStefan Roese2008-01-05-44/+0
| | | | | | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
| * | ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setupStefan Roese2008-01-05-15/+37
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Add functionality to GPIO supportLawrence R. Johnson2008-01-04-23/+40
|/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch makes two additions to GPIO support: First, it adds function gpio_read_in_bit() to read the a bit from the GPIO Input Register (GPIOx_IR) in the same way that function gpio_read_out_bit() reads a bit from the GPIO Output Register (GPIOx_OR). Second, it modifies function gpio_set_chip_configuration() to provide an additional option for configuring the GPIO from the "CFG_4xx_GPIO_TABLE". According to the 440EPx User's Manual, when an alternate output is used, the three-state control is configured in one of two ways, depending on the particular output. The first option is to select the corresponding alternate three-state control in the GPIOx_TRSH/L registers. The second option is to select the GPIO Three-State Control Register (GPIOx_TCR) in the GPIOx_TRSH/L registers, and set the corresponding bit in the GPIOx_TCR register to enable the output. For example, the Manual specifies configuring the GPIO00 Alternate 1 Signal (PreAddr07) to use the alternate three-state control (first option), and specifies configuring the GPIO32 Alternate 1 Signal (USB2OM0) with the output enabled in the GPIOx_TCR register (second option). Currently, gpio_set_chip_configuration() configures all alternate signal outputs to use the first option. This patch allow the second option to be selected by setting the "out_val" element in the table entry to "GPIO_OUT_1". The first option is used when the "out_val" element is set to "GPIO_OUT_0". Because "out_val" is not currently used when an alternate signal is selected, and because all current GPIO tables set "out_val" to "GPIO_OUT_0" for all alternate signals, this patch should not change any existing configurations. Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Enable 405EP PCI arbiter per default on all boardsStefan Roese2007-12-28-0/+5
| | | | | | | | | | In an attmemt to clean up the 4xx start.S file, I removed the enabling of the internal 405EP PCI arbiter. This is needed for multiple other 405EP platforms, like most of the esd 405EP. Now the internal PCI arbiter is enabled again per default as it has been before. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP)Stefan Roese2007-12-28-1/+1
| | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* Add denali_data_eye.o and denali_spd_ddr2.o to PPC4xx MakefileLarry Johnson2007-12-27-0/+2
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* Add 440EPx DDR2 SPD DIMM supportLarry Johnson2007-12-27-0/+1254
| | | | | | | | | | | | | This patch adds SPD DDR2 support for the 440EPx ("Denali") SDRAM controller. It should also work on the 440GRx. It is based on the DDR2 SPD code for the 440EP/440EPx, but makes no provision for DDR1 support. This code has been tested on prototype Korat boards with three Kingston DIMMS: 512 MiB ECC (one rank), 512 MiB non-ECC (one rank) and 1 GiB ECC (two ranks). The Korat board has a single DIMM socket, but support has been provided (though not tested) for boards with two DIMM sockets. Signed-off-by: Larry Johnson <lrj@acm.org>
* Copy 440EPx/GRx SDRAM data-eye search to common directoryLarry Johnson2007-12-27-0/+396
| | | | | | | | This patch creates a non-board-specific file for performing the SDRAM data-eye search. It also adds ECC error checking to the test of valid data on readback when ECC is enabled. Signed-off-by: Larry Johnson <lrj@acm.org>
* Add Ethernet 1000BASE-X support for PPC4xxLarry Johnson2007-12-27-52/+114
| | | | | | | | | | This patch adds a new switch: "CONFIG_PHY_DYNAMIC_ANEG". When this symbol is defined, the PHY will advertise it's capabilities for autonegotiation based on the capabilities shown in the PHY's status registers, including 1000BASE-X. When "CONFIG_PHY_DYNAMIC_ANEG" is not defined, the PHY will advertise hard-coded capabilities, as before. Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: fdt: Cleanup setup of cpu node setupStefan Roese2007-12-27-3/+4
| | | | | | | | | Now the cpu node setup ("timebase-frequency" and "clock-frequency") is without using the absolute path to the cpu node. This makes it possible to use this U-Boot version with both versions of cpu-node naming "cpu@0" and the former "PowerPC,440EPx@0". Signed-off-by: Stefan Roese <sr@denx.de>
* Fix ppc4xx clear_bss() codeAnatolij Gustschin2007-12-27-4/+13
| | | | | | | | ppc4xx clear_bss() fails if BSS segment size is not divisible by 4 without remainder. This patch provides fix for this problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* PPC4xx: Minimal changes to add vxWorks supportNiklaus Giger2007-12-27-1/+5
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: fix flush + invalidate_dcache_range argumentsMatthias Fuchs2007-12-27-3/+3
| | | | | | | flush + invalidate_dcache_range() expect the start and stop+1 address. So the stop address is the first address behind (!) the range. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: fdt: use fdt_fixup_ethernet()Stefan Roese2007-12-27-71/+2
| | | | | | | | | By using aliases in the dts file, the ethernet node fixup is much easier with the recently added functions. Please note that the dts file needs the aliases for this to work. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Bring 4xx fdt support up-to-dateStefan Roese2007-12-27-80/+34
| | | | | | | | This patch update the 4xx fdt support. It enabled fdt booting on the AMCC Kilauea and Sequoia for now. More can follow later quite easily. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correct GPIO offset in gpio_config()Stefan Roese2007-12-11-1/+1
| | | | | | Thanks to Gary Jennejohn for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correct 405EX PCIe UTL register mappingStefan Roese2007-11-18-3/+3
| | | | | | Map 4k mem space for UTL registers for each port. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 405EX PCIe UTL register configurationStefan Roese2007-11-16-4/+42
| | | | | | | | Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-78/+62
| | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 405EX PCIe UTLSET register setupStefan Roese2007-11-13-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make USB working with CONFIG_4xx_DCACHE definedMatthias Fuchs2007-11-09-1/+17
| | | | | | | | | | This patch disables the 44x d-cache on 'usb start' and reenables it on 'usb stop'. This should be seen as a temporary fix until the generic usb-ohci driver can life with d-cache enabled. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove redundant code from 4xx network driverMatthias Fuchs2007-11-09-5/+3
| | | | | | | | This patch removes some redundant code and decrements the end address of cache flush and invalidate by 1. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make output a little shorter on I2C bootrom detectionStefan Roese2007-11-09-34/+19
| | | | | | | | | | | Most 4xx PPC capable of using an I2C bootrom for bootstrap setting already print a line with the information which I2C bootrom is used for bootstrap configuration. So we don't need this extra line with "I2C boot EEPROM en-/dis-abled". This patch also has a little code cleanup integrated. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-8/+5
| | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change 4xx ethernet driver to handle cached memory tooStefan Roese2007-10-31-75/+62
| | | | | | | This patch enables the 4xx EMAC driver to work too, when dcache is enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add change_tlb function to modify I attribute of TLB(s)Stefan Roese2007-10-31-1/+87
| | | | | | | This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rework 4xx cache supportStefan Roese2007-10-31-135/+290
| | | | | | | New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change autonegotiation timeout from 4 to 5 secondsStefan Roese2007-10-31-1/+1
| | | | | | | | I lately noticed, that newer 4xx board with GBit support sometimes don't finish link autonegotiation in 4 seconds. Changing this timeout to 5 seconds seems fine here. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Change 4xx_enet & miiphy to use out_be32() and friendsStefan Roese2007-10-31-73/+74
| | | | | | | This patch changes all in32/out32 calls to use the recommended in_be32/ out_be32 macros instead. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correct UART input clock calculation and passing to fdtStefan Roese2007-10-31-5/+7
| | | | | | | | We now use a value in the gd (global data) structure for the UART input frequency, since the PPC4xx_SYS_INFO struct is always rewritten completely in get_sys_info(). Signed-off-by: Stefan Roese <sr@denx.de>
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