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* ppc4xx: Fix crash on sequoia with cache enabledAnatolij Gustschin2008-04-18-1/+3
| | | | | | | | | | | Currently U-Boot crashes on sequoia board in CPU POST if cache is enabled (CONFIG_4xx_DCACHE defined). The cache won't be disabled by change_tlb before CPU POST because there is an insufficient adress range check since CFG_MEM_TOP_HIDE was introduced. This patch tries to fix this problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* ppc4xx: program_tlb now uses 64bit physical addessStefan Roese2008-03-15-13/+14
| | | | | | | | This patch changes the physical addess parameter from 32bit to 64bit. This is needed for 36bit 4xx platforms to access areas located beyond the 4GB border, like SoC peripherals (EBC etc.). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add change_tlb function to modify I attribute of TLB(s)Stefan Roese2007-10-31-1/+87
| | | | | | | This function is used to either turn cache on or off in a specific memory area. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add remove_tlb() function to remove a mem area from TLB setupStefan Roese2007-07-16-1/+61
| | | | | | | | | | The new function remove_tlb() can be used to remove the TLB's used to map a specific memory region. This is especially useful for the DDR(2) setup routines which configure the SDRAM area temporarily as a cached area (for speedup on auto-calibration and ECC generation) and later need this area uncached for normal usage. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix problem with extended program_tlb() funtionStefan Roese2007-06-22-0/+8
| | | | | | | | | The recently extended program_tlb() function had a problem when multiple TLB's had to be setup (for example with 512MB of SDRAM). The virtual address was not incremented. This patch fixes this issue and is tested on Katmai with 512MB SDRAM. Signed-off-by: Stefan Roese <sr@denx.de>
* [ppc4xx] Extend program_tlb() with virtual & physical addressesStefan Roese2007-06-14-33/+44
| | | | | | | | | Now program_tlb() allows to program a TLB (or multiple) with different virtual and physical addresses. With this change, now one physical region (e.g. SDRAM) can be mapped 2 times, once with caches diabled and once with caches enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-03-01-3/+3
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| * Minor code cleanup.Wolfgang Denk2007-02-27-3/+3
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* | [PATCH] Update AMCC Katmai 440SPe eval board supportStefan Roese2007-03-01-2/+2
|/ | | | | | | | | | | This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-0/+184
This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
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