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* Dual-license IBM code contributionsJosh Boyer2009-08-09-0/+2
| | | | | | | | | | | | | It was brought to our attention that U-Boot contains code derived from the IBM OpenBIOS source code originally provided with some of the older PowerPC 4xx development boards. As a result, the original license of this code has been carried in the various files for a number of years in the U-Boot project. IBM is dual-licensing the IBM code contributions already present in U-Boot under either the terms of the GNU General Public License version 2, or the original code license already present. Signed-off-by: Josh Boyer <jwboyer@linux.vnet.ibm.com>
* ppc4xx: Replace 4xx lowercase SPR referencesMatthias Fuchs2009-07-24-103/+103
| | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix TLB reset problem with recent 44x imagesStefan Roese2009-07-24-2/+7
| | | | | | | | | | | | | | | | | Patch d873133f [ppc4xx: Add Sequoia RAM-booting target] broke "normal" booting on some 44x platforms. This breakage is only noticed in some cases while powercycling. As it seems, the code in question in start.S didn't invalidate TLB #0. This makes sense since this TLB is used for the bootrom mapping. With the patch mentioned above even TLB #0 got invalidated resulting in an error later on. This patch now fixes this issue by only invalidating TLB #0 in the RAM- booting case. Tested succesfully on Sequoia and Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de> Cc: Dirk Eibach <Eibach@gdsys.de>
* ppc4xx: Make pll_write globalMatthias Fuchs2009-07-08-0/+1
| | | | | | | | | | | | | | This patch makes pll_write on PPC405EP boards global and callable from C code. pll_write can be used to dynamically modify the PLB:PCI divider as it is required for 33/66 MHz pci adapters based on the 405EP. board_early_init_f() is a good place to do that (check M66EN signal and call pll_write() when it is required). Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Sequoia RAM-booting targetStefan Roese2009-06-12-6/+27
| | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds another build target for the AMCC Sequoia PPC440EPx eval board. This RAM-booting version is targeted for boards without NOR FLASH (NAND booting) which need a possibility to initially program their NAND FLASH. Using a JTAG debugger (e.g. BDI2000/3000) configured to setup the SDRAM, this debugger can load this RAM- booting image to the target address in SDRAM (in this case 0x1000000) and start it there. Then U-Boot's standard NAND commands can be used to program the NAND FLASH (e.g. "nand write ..."). Here the commands to load and start this image from the BDI2000: 440EPX>reset halt 440EPX>load 0x1000000 /tftpboot/sequoia/u-boot.bin 440EPX>go 0x1000000 Please note that this image automatically scans for an already initialized SDRAM TLB (detected by EPN=0). This TLB will not be cleared. This TLB doesn't need to be TLB #0, this RAM-booting version will detect it and preserve it. So booting via BDI2000 will work and booting with a complete different TLB init via U-Boot works as well. Signed-off-by: Stefan Roese <sr@denx.de>
* Coding style cleanup, update CHANGELOG.Wolfgang Denk2008-12-16-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-1/+2
| | | | | | | Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc4xx: Changed 460EX/GT OCM TLB and internal SRAM initializationDave Mitchell2008-11-21-7/+20
| | | | | | | | | | | | | | | | | | Expanded OCM TLB to allow access to 64K OCM as well as 256K of internal SRAM. Adjusted internal SRAM initialization to match updated user manual recommendation. OCM & ISRAM are now mapped as follows: physical virtual size ISRAM 0x4_0000_0000 0xE300_0000 256k OCM 0x4_0004_0000 0xE304_0000 64k A single TLB was used for this mapping. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Added ppc4xx-isram.h for internal SRAM and L2 cache DCRsDave Mitchell2008-11-21-20/+21
| | | | | | | | | | | Added include/asm-ppc/ppc4xx-isram.h and moved internal SRAM and L2 cache DCRs from ppc440.h to this new header. Also converted these DCR defines from lowercase to uppercase and modified referencing modules to use them. Signed-off-by: Dave Mitchell <dmitch71@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Clear all potentially pending exceptions in MCSRStefan Roese2008-11-20-0/+4
| | | | | | | | This is needed on Canyonlands which still has an exception pending while running relocate_code(). This leads to a failure after trap_init() is moved to the top of board_init_r(). Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Generic architecture for xilinx ppc405(v3)Ricardo Ribalda Delgado2008-10-24-1/+2
| | | | | | | | | | | | | | | | | As "ppc44x: Unification of virtex5 pp440 boards" did for the xilinx ppc440 boards, this patch presents a common architecture for all the xilinx ppc405 boards. Any custom xilinx ppc405 board can be added very easily with no code duplicity. This patch also adds a simple generic board, that can be used on almost any design with xilinx ppc405 replacing the file ppc405-generic/xparameters.h This patch is prepared to work with the latest version of EDK (10.1) Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda@uam.es> Signed-off-by: Stefan Roese <sr@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-172/+172
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Add initial 460SX defines for the cpu/ppc4xx directory.Feng Kan2008-07-11-2/+17
| | | | | Signed-off-by: Feng Kan <fkan@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove superfluous dram_init() call or replace it by initdram()Stefan Roese2008-06-03-6/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | Historically the 405 U-Boot port had a dram_init() call in early init stage. This function was still called from start.S and most of the time coded in assembler. This is not needed anymore (since a long time) and boards should implement the common initdram() function in C instead. This patch now removed the dram_init() call from start.S and removes the empty implementations that are scattered through most of the 405 board ports. Some older board ports really implement this dram_init() though. These are: csb272 csb472 ERIC EXBITGEN W7OLMC W7OLMG I changed those boards to call this assembler dram_init() function now from their board specific initdram() instead. This *should* work, but please test again on those platforms. And it is perhaps a good idea that those boards use some common 405 SDRAM initialization code from cpu/ppc4xx at some time. So further patches welcome here. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx/NAND_SPL: Consolidate 405 and 440 NAND booting code in start.SStefan Roese2008-06-03-126/+80
| | | | | | | | | | | | | | | | | This patch consolidates the 405 and 440 parts of the NAND booting code selected via CONFIG_NAND_SPL. Now common code is used to initialize the SDRAM by calling initdram() and to "copy/relocate" to SDRAM/OCM/etc. Only *after* running from this location, nand_boot() is called. Please note that the initsdram() call is now moved from nand_boot.c to start.S. I experienced problems with some boards like Kilauea (405EX), which don't have internal SRAM (OCM) and relocation needs to be done to SDRAM before the NAND controller can get accessed. When initdram() is called later on in nand_boot(), this can lead to problems with variables in the bss sections like nand_ecc_pos[]. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Scott Wood <scottwood@freescale.com>
* ppc4xx: Enable Primordial Stack for 40x and Unify ECC HandlingGrant Erickson2008-06-03-79/+235
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-29/+29
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Complete remove bogus dflush()Stefan Roese2008-04-29-29/+0
| | | | | | | | | | Since the current dflush() implementation is know to have some problems (as seem on lwmon5 ECC init) this patch removes it completely and replaces it by using clean_dcache_range(). Tested on Katmai with ECC DIMM. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add Canyonlands NAND booting supportStefan Roese2008-03-15-1/+7
| | | | | | | | | | | | | | | 460EX doesn't support a fixed bootstrap option to boot from 512 byte page NAND devices. The only bootstrap option for NAND booting is option F for 2k page devices. So to boot from a 512 bype page device, the I2C bootstrap EEPROM needs to be programmed accordingly. This patch adds basic NAND booting support for the AMCC Canyonlands aval board and also adds support to the "bootstrap" command, to enable NAND booting I2C setting. Tested with 512 byte page NAND device (32MByte) on Canyonlands. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)Stefan Roese2008-03-15-2/+9
| | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge branch 'master' of git://www.denx.de/git/u-boot-ppc4xxWolfgang Denk2008-02-15-0/+4
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| * ppc4xx: Fix problem with init-ram bigger than 4k on 440 platformsStefan Roese2008-02-04-0/+4
| | | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-33/+0
|/ | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* ppc4xx: Fix dflush() to restore DVLIM registerLarry Johnson2008-01-10-0/+2
| | | | Signed-off-by: Larry Johnson <lrj@acm.org>
* ppc4xx: Add 44x cache locking to better support init-ram in d-cacheStefan Roese2008-01-09-0/+52
| | | | | | | | | | | This patch adds support for locking the init-ram/stack in d-cache, so that other regions may use d-cache as well Note, that this current implementation locks exactly 4k of d-cache, so please make sure that you don't define a bigger init-ram area. Take a look at the lwmon5 440EPx implementation as a reference. Signed-off-by: Stefan Roese <sr@denx.de>
* Fix ppc4xx clear_bss() codeAnatolij Gustschin2007-12-27-4/+13
| | | | | | | | ppc4xx clear_bss() fails if BSS segment size is not divisible by 4 without remainder. This patch provides fix for this problem. Signed-off-by: Anatolij Gustschin <agust@denx.de>
* PPC4xx: Minimal changes to add vxWorks supportNiklaus Giger2007-12-27-1/+5
| | | | Signed-off-by: Niklaus Giger <niklaus.giger@netstal.com>
* ppc4xx: Rework 4xx cache supportStefan Roese2007-10-31-123/+21
| | | | | | | New cache handling functions added and all existing functions moved from start.S into seperate cache.S. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add PPC405EX supportStefan Roese2007-10-31-30/+39
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add initial Zeus (PPC405EP) board supportStefan Roese2007-08-14-32/+16
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add support for AMCC 405EP Taihu boardJohn Otken2007-07-26-0/+33
| | | | Signed-off-by: John Otken <john@softadvances.com>
* Coding style cleanup; update CHANGELOG.Wolfgang Denk2007-07-10-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merged POST framework with the current TOT.Sergei Poselenov2007-07-05-0/+8
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* [ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski2007-06-22-1/+0
| | | | | - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
* Coding style cleanup. Refresh CHANGELOG.Wolfgang Denk2007-06-20-103/+104
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* [ppc4xx] Fix problem with NAND booting on AMCC AcadiaStefan Roese2007-06-19-3/+3
| | | | | | | | The latest changes showed a problem with the location of the NAND-SPL image in the OCM and the init-data area (incl. cache). This patch fixes this problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Clean up 440 exceptions handlingGrzegorz Bernacki2007-06-15-162/+167
| | | | | | | | | | | | | | | | | | | | | | - Introduced dedicated switches for building 440 and 405 images required for 440-specific machine instructions like 'rfmci' etc. - Exception vectors moved to the proper location (_start moved away from the critical exception handler space, which it occupied) - CriticalInput now serviced (with default handler) - MachineCheck properly serviced (added a dedicated handler and return subroutine) - Overall cleanup of exceptions declared with STD_EXCEPTION macro (unused, unhandled and those not relevant for 4xx were eliminated) - Eliminated Linux leftovers, removed dead code Signed-off-by: Grzegorz Bernacki <gjb@semihalf.com> Signed-off-by: Rafal Jaworowski <raj@semihalf.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add NAND booting support for AMCC Acadia (405EZ) eval boardStefan Roese2007-06-06-17/+55
| | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Acadia eval board. Please make sure to configure jumper J7 to position 2-3 when booting from NOR, and to position 1-2 when booting for NAND. I also added a board command to configure the I2C bootstrap EEPROM values. Right now only 267MHz is support for booting either via NOR or NAND FLASH. Here the usage: => bootstrap 267 nor ;to configure the board for 267MHz NOR booting => bootstrap 267 nand ;to configure the board for 267MHz NNAND booting Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/stefan/git/u-boot/bamboo-nandStefan Roese2007-06-01-92/+129
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| * ppc4xx: Add NAND booting support for AMCC Bamboo (440EP) eval boardStefan Roese2007-06-01-92/+129
| | | | | | | | | | | | | | | | | | | | This patch adds NAND booting support for the AMCC Bamboo eval board. Since the NAND-SPL boot image is limited to 4kbytes, this version only supports the onboard 64MBytes of DDR. The DIMM modules can't be supported, since the setup code for I2C DIMM autodetection and configuration is too big for this NAND bootloader. Signed-off-by: Stefan Roese <sr@denx.de>
* | ppc4xx: Fix small 405EZ OCM initilization bug in start.SStefan Roese2007-05-24-1/+1
| | | | | | | | | | | | | | | | As pointed out by Bruce Adler <bruce.adler@acm.org> this patch fixes a small bug in the 405EZ OCM initialization. Thanks for spotting. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xxWolfgang Denk2007-04-18-27/+27
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| * Merge with /home/git/u-bootWolfgang Denk2007-03-08-1/+1
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| * | Some code cleanup.Wolfgang Denk2007-03-04-36/+36
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* | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-24-42/+9
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| * | | [PATCH] Clean up 40EZ/Acadia supportStefan Roese2007-03-24-42/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch cleans up all the open issue of the preliminary Acadia support. Signed-off-by: Stefan Roese <sr@denx.de>
* | | | Merge with /home/stefan/git/u-boot/acadiaStefan Roese2007-03-21-5/+72
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| * | [PATCH] Add AMCC PPC405EZ supportStefan Roese2007-03-21-5/+72
| |/ | | | | | | | | | | | | | | | | | | This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-1/+1
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| * | [PATCH] Update AMCC Luan 440SP eval board supportStefan Roese2007-03-08-1/+1
| |/ | | | | | | | | | | | | | | | | | | | | | | | | | | | | The AMCC Luan now uses the common 440SP(e) DDR SPD code for DDR inititializition. This includes DDR auto calibration and support for different DIMM modules, instead of the fixed setup used in the earlier version. This patch also enables the cache in FLASH for the startup phase of U-Boot (while running from FLASH). After relocating to SDRAM the cache is disabled again. This will speed up the boot process, especially the SDRAM setup, since there are some loops for memory testing (auto calibration). Signed-off-by: Stefan Roese <sr@denx.de>
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