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* ppc4xx: Add function to check and dynamically change PCI sync clockStefan Roese2009-10-23-0/+69
| | | | | | | | | | | | | | | | | | PPC440EP(x)/PPC440GR(x): In asynchronous PCI mode, the synchronous PCI clock must meet certain requirements. The following equation describes the relationship that must be maintained between the asynchronous PCI clock and synchronous PCI clock. Select an appropriate PCI:PLB ratio to maintain the relationship: AsyncPCIClk - 1MHz <= SyncPCIclock <= (2 * AsyncPCIClk) - 1MHz This patch now adds a function to check and reconfigure the sync PCI clock to meet this requirement. This is in preparation for some AMCC boards (Sequoia/Rainier and Yosemite/Yellowstone) using this function to not violate the PCI clocking rules. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc_4xx: Apply new HW register namesNiklaus Giger2009-10-07-2/+2
| | | | | | | | Modify all existing *.c files to use the new register names as seen in the AMCC manuals. Signed-off-by: Niklaus Giger <niklaus.giger@member.fsf.org> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Big cleanup of PPC4xx definesStefan Roese2009-09-11-34/+34
| | | | | | | | | | | | | | | | This patch cleans up multiple issues of the 4xx register (mostly DCR, SDR, CPR, etc) definitions: - Change lower case defines to upper case (plb4_acr -> PLB4_ACR) - Change the defines to better match the names from the user's manuals (e.g. cprpllc -> CPR0_PLLC) - Removal of some unused defines Please test this patch intensive on your PPC4xx platform. Even though I tried not to break anything and tested successfully on multiple 4xx AMCC platforms, testing on custom platforms is recommended. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Replace 4xx lowercase SPR referencesMatthias Fuchs2009-07-24-1/+1
| | | | | Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Move 405EP pci code from cpu_init_f() to __pci_pre_init()Matthias Fuchs2009-07-10-5/+0
| | | | | | | | | | | | | | | | | | | | This patch moves some basic PCI initialisation from the 4xx cpu_init_f() to cpu/ppc4xx/4xx_pci.c. The original cpu_init_f() function enabled the 405EP's internal arbiter in all situations. Also the HCE bit in cpc0_pci is always set. The first is not really wanted for PCI adapter designs and the latter is a general bug for PCI adapter U-Boots. Because it enables PCI configuration by the system CPU even when the PCI configuration has not been setup by the 405EP. The one and only correct place is in pci_405gp_init() (see "Set HCE bit" comment). So for compatibility reasons the arbiter is still enabled in any case, but from weak pci_pre_init() so that it can be replaced by board specific code. Signed-off-by: Matthias Fuchs <matthias.fuchs@esd.eu> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Don't write the MAC address into the internal SoC registersStefan Roese2009-03-20-28/+1
| | | | | | | Remove this code. It's not needed. The 4xx EMAC driver stores the MAC addresses into the SoC registers instead. Signed-off-by: Stefan Roese <sr@denx.de>
* cpu/: get mac address from environmentMike Frysinger2009-03-20-6/+8
| | | | | | | | | | | | | | | | | | | The environment is the canonical storage location of the mac address, so we're killing off the global data location and moving everything to querying the env directly. The cpus that get converted here: at91rm9200 mpc512x mpc5xxx mpc8260 mpc8xx ppc4xx Signed-off-by: Mike Frysinger <vapier@gentoo.org> CC: Ben Warren <biggerbadderben@gmail.com> CC: John Rigby <jrigby@freescale.com> CC: Stefan Roese <sr@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-50/+50
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: Cleanup of "ppc4xx: Optimize PLB4 Arbiter..." patchStefan Roese2008-08-21-9/+8
| | | | | | | | | | | | | This patch fixes some minor issues introduced with the patch: ppc4xx: Optimize PLB4 Arbiter... from Prodyut Hazarika: - Rework memory-queue and PLB arbiter optimization code, that the local variable is not needed anymore. This removes one #ifdef. - Use consistant spacing in ppc4xx.h header (XXX + 0x01 instead of XXX+ 0x01). This was not introduced by Prodyut, just a copy-paste problem. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Optimize PLB4 Arbiter and Memory Queue settings for PPC440SP/SPe,Prodyut Hazarika2008-08-21-1/+15
| | | | | | | | | | | | | | | PPC405EX and PPC460EX/GT/SX - Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors - Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors (405 and 440/460) - Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors - Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Rework 440GX UIC handlingStefan Roese2008-07-11-1/+14
| | | | | | | | | | | | | This patch reworks the 440GX interrupt handling so that the common 4xx code can be used. The 440GX is an exception to all other 4xx variants by having the cascading interrupt vectors not on UIC0 but on a special UIC named UICB0 (UIC Base 0). With this patch now, U-Boot references the 440GX UICB0 when UIC0 is selected. And the common 4xx interrupt handling is simpler without any 440GX special cases. Also some additional cleanup to cpu/ppc4xx/interrupt.c is done. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 460EX errata with CPU lockup upon high AHB trafficStefan Roese2008-06-30-2/+18
| | | | | | | | | | | | | | | This patch implements a fix provided by AMCC so that the lockup upon simultanious traffic on AHB USB OTG, USB 2.0 and SATA doesn't occur anymore: Set SDR0_AHB_CFG[A2P_INCR4] (bit 24) and clear SDR0_AHB_CFG[A2P_PROT2] (bit 25) for a new 460EX errata regarding concurrent use of AHB USB OTG, USB 2.0 host and SATA. This errata is not officially available yet. I'll update the comment to add the errata number later. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable Primordial Stack for 40x and Unify ECC HandlingGrant Erickson2008-06-03-85/+0
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch (Part 1 of 2): * Rolls up a suite of changes to enable correct primordial stack and global data handling when the data cache is used for such a purpose for PPC40x-variants (i.e. CFG_INIT_DCACHE_CS). * Related to the first, unifies DDR2 SDRAM and ECC initialization by eliminating redundant ECC initialization implementations and moving redundant SDRAM initialization out of board code into shared 4xx code. * Enables MCSR visibility on the 405EX(r). * Enables the use of the data cache for initial RAM on both AMCC's Kilauea and Makalu and removes a redundant CFG_POST_MEMORY flag from each board's CONFIG_POST value. - Removed, per Stefan Roese's request, defunct memory.c file for Makalu and rolled sdram_init from it into makalu.c. With respect to the 4xx DDR initialization and ECC unification, there is certainly more work that can and should be done (file renaming, etc.). However, that can be handled at a later date on a second or third pass. As it stands, this patch moves things forward in an incremental yet positive way for those platforms that utilize this code and the features associated with it. Signed-off-by: Grant Erickson <gerickson@nuovations.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: PPC405EP Set EMAC noise filter bitsMarkus Brunner2008-03-27-1/+1
| | | | | | | | | This bug was introduced with commit aee747f19b460a0e9da20ff21e90fdaac1cec359 which enabled CFG_4xx_GPIO_TABLE for PPC405 and unintentionally disabled the setting of the emac noise filter bits for PPC405EP when CFG_4xx_GPIO_TABLE is set. Signed-off-by: Markus Brunner <super.firetwister@gmail.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Reconfigure PLL for 667MHz processor for PPC440EPxMike Nuss2008-03-27-1/+99
| | | | | | | | | | | | On PPC440EPx without a bootstrap I2C EEPROM, the PLL can be reconfigured after startup to change the speed of the clocks. This patch adds the option CFG_PLL_RECONFIG. If this option is set to 667, the CPU initialization code will reconfigure the PLL to run the system with a CPU frequency of 667MHz and PLB frequency of 166MHz, without the need for an external EEPROM. Signed-off-by: Mike Nuss <mike@terascala.com> Acked-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add basic support for AMCC 460EX/460GT (2/5)Stefan Roese2008-03-15-0/+1
| | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 405EP PCI arbiter per default on all boardsStefan Roese2007-12-28-0/+5
| | | | | | | | | | In an attmemt to clean up the 4xx start.S file, I removed the enabling of the internal 405EP PCI arbiter. This is needed for multiple other 405EP platforms, like most of the esd 405EP. Now the internal PCI arbiter is enabled again per default as it has been before. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Fix bug in cpu_init.c (405EP instead of 450EP)Stefan Roese2007-12-28-1/+1
| | | | | Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Matthias Fuchs <matthias.fuchs@esd-electronics.com>
* ppc4xx: Enable 440 GPIO init table CFG_440_GPIO_TABLE for 405 platformsStefan Roese2007-11-15-3/+3
| | | | | | | | - Rename CFG_440_GPIO_TABLE to CFG_4xx_GPIO_TABLE - Cleanup of the 4xx GPIO functions - Move some GPIO defines from the cpu headers ppc405.h/ppc440.h into gpio.h Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add PPC405EX supportStefan Roese2007-10-31-3/+11
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-1/+1
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* Extend POST support for PPC440Igor Lisitsin2007-06-22-0/+2
| | | | | | | Added memory, CPU, UART, I2C and SPR POST tests for PPC440. Signed-off-by: Igor Lisitsin <igor@emcraft.com> --
* [PATCH] Add 4xx GPIO functionsStefan Roese2007-03-24-113/+2
| | | | | | | This patch adds some 4xx GPIO functions. It also moves some of the common code and defines into a common 4xx GPIO header file. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add AMCC PPC405EZ supportStefan Roese2007-03-21-1/+2
| | | | | | | | | | This patch adds support for the new AMCC 405EZ PPC. It is in preparation for the AMCC Acadia board support. Please note that this Acadia/405EZ support is still in a beta stage. Still lot's of cleanup needed but we need a preliminary release now. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Add support for the AMCC Katmai (440SPe) eval boardStefan Roese2007-02-20-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Fix: Compilerwarnings for SC3 board.Heiko Schocher2007-01-18-3/+2
| | | | | | | The EBC Configuration Register is now by CFG_EBC_CFG definable Added JFFS2 support for the SC3 board. Signed-off-by: Heiko Schocher <hs@denx.de>
* Merge with /home/hs/SC3/u-bootWolfgang Denk2007-01-15-2/+9
|\ | | | | | | Some code cleanup.
| * Added support for the SOLIDCARD III board from EurodesignHeiko Schocher2007-01-11-1/+4
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
* | [PATCH] Add DDR2 optimization code for Sequoia (440EPx) boardStefan Roese2007-01-05-3/+0
|/ | | | | | | | | | This code will optimize the DDR2 controller setup on a board specific basis. Note: This code doesn't work right now on the NAND booting image for the Sequoia board, since it doesn't fit into the 4kBytes for the SPL image. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] Update Prodrive ALPR board support (440GX)Stefan Roese2006-11-27-0/+4
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* * PPC405EP: Add CFG_GPIO0_OR, CFG_GPIO0_ODR to setup GPIO completely.Stefan Roese2006-10-12-4/+10
| | | | | | - Add configuration of Open Drain GPIO Output selection - Add configuration of initial value of GPIO output pins Patch by Tolunay Orkun, 07 Apr 2006
* Add support for PCS440EP boardStefan Roese2006-06-02-1/+119
| | | | Patch by Stefan Roese, 02 Jun 2006
* GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk2006-03-31-2/+4
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* Merged 405gp_enet.c and 440gx_enet.c to generic 4xx_enet.cStefan Roese2005-08-16-1/+1
| | | | | now handling all 4xx cpu's. Patch by Stefan Roese, 16 Aug 2005
* Changed CONFIG_440_xx to CONFIG_440xx for a consistent design (405 and linux)Stefan Roese2005-08-08-1/+1
| | | | Patch by Stefan Roese, 08 Aug 2005
* Add support for AMCC PPC440EP/GR eval boards Yosemite and Yellowstone.Stefan Roese2005-08-01-0/+4
| | | | Patch by Steven Blakeslee, 27 Jul 2005
* - Fix bug for initial stack in data cache as pointed out by Thomas Schaefer ↵stroese2003-06-05-7/+92
| | | | (tschaefer@giga-stream.de). Now inital stack in data cache can be used even if the chip select is in use.
* PPC405EP support added.stroese2003-05-23-3/+24
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* Changed PPC405GPr version from A to B.stroese2003-04-04-1/+1
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* Set edge conditioning circuitry on PPC405GPr for compatibility to existing ↵stroese2003-03-20-0/+10
| | | | PPC405GP designs.
* Initial revisionwdenk2002-08-27-0/+148
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