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* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-13-1298/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* Replace "#include <asm-$ARCH/$FILE>" with "#include <asm/$FILE>"Peter Tyser2010-04-13-1/+1
| | | | | | | | | | The appropriate include/asm-$ARCH directory should already by symlinked to include/asm so using the whole "asm-$ARCH" path is unnecessary. This change should also allow us to move the include/asm-$ARCH directories into their appropriate lib/$ARCH/ directories. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* PCIe, USB: Replace 'end point' references with 'endpoint'Peter Tyser2010-01-17-2/+2
| | | | | | | | | When referring to PCIe and USB 'endpoint' is the standard naming convention. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Remy Bohmer <linux@bohmer.net>
* ppc4xx: Remove some testing code from 4xx_pcie.cStefan Roese2009-11-23-4/+0
| | | | | | This code got included accidentally. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate 4xx PCIe board specific configurationStefan Roese2009-11-09-0/+123
| | | | | | | | | This patch consolidates the PPC4xx board specific PCIe configuration code. This way the duplicated code is removed. Boards can implement a special, non standard behaviour (e.g. number of PCIe slots, etc) by overriding the weak default functions. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix msg "initialization as root-complex failed" upon PCIe scanStefan Roese2009-10-07-1/+2
| | | | | | | | | | This message is printed upon PCIe bus scan, not only upon error, but also if no PCIe device is detected at all. Since this is not an error, let's remove this message in this case. We already have the message "link is not up." if there is no PCIe device present. Signed-off-by: Stefan Roese <sr@denx.de> Acked-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Fix PCIE PLL lock on 440SPe Yucca boardRupjyoti Sarmah2009-09-23-8/+15
| | | | | | | | | | u-boot reports a PCIE PLL lock error at boot time on Yucca board, and left PCIe nonfunctional. This is fixed by making u-boot function ppc4xx_init_pcie() to wait 300 uS after negating reset before the first check of the PLL lock. Signed-off-by: Rupjyoti Sarmah <rsarmah@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: PCIe: Change 16GB inbound memory to 4GBStefan Roese2009-02-18-2/+2
| | | | | | | This patch fixes a problem recently seen on some 4xx platforms. For example on Kilauea PCIe slot #0. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make PCIE support selectableDirk Eibach2009-02-06-1/+1
| | | | | | | | | On some platforms PCIE support is not required, but would be included because the cpu supports it. To reduce fooprint it is now configurable via CONFIG_PCI_DISABLE_PCIE. Signed-off-by: Dirk Eibach <eibach@gdsys.de> Signed-off-by: Stefan Roese <sr@denx.de>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-72/+72
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* ppc4xx: AMCC PPC460GT/EX PCI-E de-emphasis adjustment fixTirumala R Marri2008-08-22-5/+5
| | | | | | | | | | | During recent PCI-E tests it has been found that current driverl level and de-emphasis values are not set correctly. After sweeping throgh all de-ephasis values, it was found that 0x130 is a right value. Where 0x13 is driver level and 0 is de-emphasis. Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix include sequence in 4xx_pcie.cStefan Roese2008-07-11-3/+3
| | | | | | | | | This patch now moves common.h to the top of the inlcude list. This is needed for boards with CONFIG_PHYS_64BIT set (e.g. katmai), so that the phys_size_t/phys_addr_t are defined to the correct size in this driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 460EX/GT PCIe port initializationStefan Roese2008-07-01-7/+5
| | | | | | | | This patch fixes a bug where the 460EX/GT PCIe UTLSET1 register was configured incorrectly. Thanks to Olga Buchonina from AMCC for pointing this out. Signed-off-by: Stefan Roese <sr@denx.de>
* Big white-space cleanup.Wolfgang Denk2008-05-21-2/+2
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc4xx: Add basic support for AMCC 460EX/460GT (1/5)Stefan Roese2008-03-15-8/+195
| | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Correct 405EX PCIe UTL register mappingStefan Roese2007-11-18-3/+3
| | | | | | Map 4k mem space for UTL registers for each port. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Enable 405EX PCIe UTL register configurationStefan Roese2007-11-16-2/+42
| | | | | | | | Till now the UTL registers on 405EX were not initialized but left with their default values. This patch new initializes some of the UTL registers on 405EX. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Fix 405EX PCIe UTLSET register setupStefan Roese2007-11-13-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add PCIe endpoint support on Kilauea (405EX)Stefan Roese2007-10-31-10/+21
| | | | | | | | | | | | This patch adds endpoint support for the AMCC Kilauea eval board. It can be tested by connecting a reworked PCIe cable (only 1x lane singles connected) to another root-complex. In this test setup, a 64MB inbound window is configured at BAR0 which maps to 0 on the PLB side. So accessing this BAR0 from the root-complex will access the first 64MB of the SDRAM on the PPC side. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Dynamic configuration of 4xx PCIe mode as root or endpoint modeStefan Roese2007-10-31-1/+21
| | | | | | | | | | | | | | | | | | | | | | | | | | | | This patch adds support for dynamic configuration of PCIe ports for the AMCC PPC4xx boards equipped with PCIe interfaces. These are the PPC440SPe boards Yucca & Katmai and the 405EX board Kilauea. This dynamic configuration is done via the "pcie_mode" environement variable. This variable can be set to "EP" or "RP" for endpoint or rootpoint mode. Multiple values can be joined via the ":" delimiter. Here an example: pcie_mode=RP:EP:EP This way, PCIe port 0 will be configured as rootpoint, PCIe port 1 and 2 as endpoint. Per default Yucca will be configured as: pcie_mode=RP:EP:EP Per default Katmai will be configured as: pcie_mode=RP:RP:REP Per default Kilauea will be configured as: pcie_mode=RP:RP Signed-off-by: Tirumala R Marri <tmarri@amcc.com> Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Change PCIe status output to match common styleStefan Roese2007-10-31-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Disable debug output as defaultStefan Roese2007-10-31-1/+1
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: More general cleanup and 405EX PCIe support addedStefan Roese2007-10-31-39/+54
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Change CFG_PCIE_MEMSIZE to 128MB on Yucca & KatmaiStefan Roese2007-10-31-1/+24
| | | | | | | | | | | | | | | | | 128MB seems to be the smallest possible value for the memory size for on PCIe port. With this change now the BAR's of the PCIe cards are accessible under U-Boot. One big note: This only works for PCIe port 0 & 1. For port 2 this currently doesn't work, since the base address is now 0xc0000000 (0xb0000000 + 2 * 0x08000000), and this is already occupied by CFG_PCIE0_CFGBASE. But solving this issue for port 2 would mean to change the base addresses completely and this change would have too much impact right now. This patch adds debug output to the 4xx pcie driver too. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: 4xx_pcie: Fix problem with SDRN access using port number as idxStefan Roese2007-10-31-6/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add a comment for 405EX PCIe endpoint configurationStefan Roese2007-10-31-0/+6
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (3)Stefan Roese2007-10-31-419/+223
| | | | | | | | | | | | | | | (3) This patch introduces macros like SDRN_PESDR_DLPSET(port) to access the SDR registers of the PCIe ports. This makes the overall design clearer, since it removed a lot of switch statements which are not needed anymore. Also, the functions ppc4xx_init_pcie_rootport() and ppc4xx_init_pcie_entport() are merged into a single function ppc4xx_init_pcie_port(), since most of the code was duplicated. This makes maintainance and porting to other 4xx platforms easier. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (2)Stefan Roese2007-10-31-10/+10
| | | | | | | | | | | This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (2) This patch renames the functions from 440spe_ to 4xx_ with a little additional cleanup Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Make 440SPe PCIe code more generic to use on different 4xx PPCs (1)Stefan Roese2007-10-31-0/+1067
This patch is the first patch of a series to make the 440SPe PCIe code usable on different 4xx PPC platforms. In preperation for the new 405EX which is also equipped with PCIe interfaces. (1) This patch renames the files from 440spe_pcie to 4xx_pcie Signed-off-by: Stefan Roese <sr@denx.de>
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