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* ppc4xx: Fix problem with DIMMs with 8 banks in 44x_spd_ddr2.cStefan Roese2008-04-30-2/+5
| | | | | | | | | This patch fixes a problem with DIMMs that have 8 banks. Now the MCIF0_MBxCF register will be setup correctly for this setup too. This was noticed with the 512MB DIMM on Canyonlands/Glacier. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Complete remove bogus dflush()Stefan Roese2008-04-29-2/+3
| | | | | | | | | | Since the current dflush() implementation is know to have some problems (as seem on lwmon5 ECC init) this patch removes it completely and replaces it by using clean_dcache_range(). Tested on Katmai with ECC DIMM. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add basic support for AMCC 460EX/460GT (1/5)Stefan Roese2008-03-15-4/+37
| | | | | | This patch adds basic support for the AMCC 460EX/460GT PPC's. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove compiler warning in cpu/ppc4xx/44x_spd_ddr2.cStefan Roese2008-01-15-2/+2
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Remove unused CONFIG_ECC_ERROR_RESET from 44x_spd_ddr2.cStefan Roese2008-01-05-44/+0
| | | | Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update Katmai/44x_spd_ddr2.c code for optimal DDR2 setupStefan Roese2008-01-05-15/+37
| | | | | | | | | | | | | | On Katmai the complete auto-calibration somehow doesn't seem to produce the best results, meaning optimal values for RQFD/RFFD. This was discovered by GDA using a high bandwidth scope, analyzing the DDR2 signals. GDA provided a fixed value for RQFD, so now on Katmai "only" RFFD is auto-calibrated. This patch also adds RDCC calibration as mentioned on page 7 of the AMCC PowerPC440SP/SPe DDR2 application note: "DDR1/DDR2 Initialization Sequence and Dynamic Tuning" Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Add CONFIG_4xx_DCACHE compile options to enable cached SDRAMStefan Roese2007-10-31-2/+2
| | | | | | | | | | | | | | This patch adds the CONFIG_4xx_DCACHE options to some SDRAM init files and to the Sequoia TLB init code. Now the cache can be enabled on 44x boards by defining CONFIG_4xx_DCACHE in the board config file. This option will disappear, when more boards use is successfully and no more known problems exist. This is tested successfully on Sequoia and Katmai. The only problem that needs to be fixed is, that USB is not working on Sequoia right now, since it will need some cache handling code too, similar to the 4xx EMAC driver. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Consolidate some of the 405 and 440 macros/structs into 4xxStefan Roese2007-10-31-15/+12
| | | | | | | | | | This patch moves some common 4xx macros and the PPC405_SYS_INFO/ PPC440_SYS_INFO structure into the common ppc4xx.h header. Lot's of other macros are good candidates to be consolidated this way in the future. Signed-off-by: Stefan Roese <sr@denx.de>
* lib_ppc: make board_add_ram_info weakKim Phillips2007-08-18-2/+0
| | | | | | | | | | | | platforms wishing to display RAM diagnostics in addition to size, can do so, on one line, in their own board_add_ram_info() implementation. this consequently eliminates CONFIG_ADD_RAM_INFO. Thanks to Stefan for the hint. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* ppc4xx: Add new weak functions to support boardspecific DDR2 configurationStefan Roese2007-07-16-14/+44
| | | | | | | The new "weak" functions ddr_wrdtr() and ddr_clktr() are added to better support non default, boardspecific DDR(2) controller configuration. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/hs/Atronic/u-bootWolfgang Denk2007-07-09-32/+42
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| * [PCS440EP] get rid of CONFIG_PPC4xx_USE_SPD_DDR_INIT_HANGHeiko Schocher2007-06-25-38/+41
| | | | | | | | Signed-off-by: Heiko Schocher <hs@denx.de>
| * [PCS440EP] upgrade the PCS440EP board:Heiko Schocher2007-06-22-32/+39
| | | | | | | | | | | | | | | | | | | | | | | | - Show on the Status LEDs, some States of the board. - Get the MAC addresses from the EEProm - use PREBOOT - use the CF on the board. - check the U-Boot image in the Flash with a SHA1 checksum. - use dynamic TLB entries generation for the SDRAM Signed-off-by: Heiko Schocher <hs@denx.de>
* | Coding stylke cleanup; rebuild CHANGELOGWolfgang Denk2007-06-22-2/+2
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* | [ppc4xx] Extend program_tlb() with virtual & physical addressesStefan Roese2007-06-14-2/+2
|/ | | | | | | | | Now program_tlb() allows to program a TLB (or multiple) with different virtual and physical addresses. With this change, now one physical region (e.g. SDRAM) can be mapped 2 times, once with caches diabled and once with caches enabled. Signed-off-by: Stefan Roese <sr@denx.de>
* ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-06-01-1/+6
| | | | | | | Add config option for 180 degree advance clock control as needed for the AMCC Luan eval board. Signed-off-by: Stefan Roese <sr@denx.de>
* Merge with /home/wd/git/u-boot/custodian/u-boot-74xx-7xxWolfgang Denk2007-04-18-1/+1
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| * Merge with /home/git/u-bootWolfgang Denk2007-03-08-25/+39
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| * | Some code cleanup.Wolfgang Denk2007-03-04-5/+5
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* | | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-03-31-19/+49
| | | | | | | | | | | | | | | | | | | | | Additional RAM information is now printed upon powerup, like DDR2 frequency and CAS latency. Signed-off-by: Stefan Roese <sr@denx.de>
* | | ppc4xx: Update 44x_spd_ddr2 code (440SP/440SPe)Stefan Roese2007-03-31-48/+81
| |/ |/| | | | | | | | | | | | | Fix a bug in the auto calibration routine. This driver now runs more reliable with the tested modules. It's also tested with 167MHz PLB frequency (667MHz DDR2 frequency) on the Katmai. Signed-off-by: Stefan Roese <sr@denx.de>
* | Merge with /home/wd/git/u-boot/custodian/u-boot-ppc4xxWolfgang Denk2007-03-08-25/+39
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| * | ppc4xx: Update 440SP/440SPe DDR SPD setup code to support 440SPStefan Roese2007-03-08-25/+39
| |/ | | | | | | Signed-off-by: Stefan Roese <sr@denx.de>
* | Restructure POST directory to support of other CPUs, boards, etc.Wolfgang Denk2007-03-06-4/+4
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* Merge with /home/stefan/git/u-boot/denx-merge-srStefan Roese2007-03-01-14/+14
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| * Minor code cleanup.Wolfgang Denk2007-02-27-17/+17
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* | [PATCH] Update AMCC Katmai 440SPe eval board supportStefan Roese2007-03-01-97/+278
|/ | | | | | | | | | | This patch updates the recently added Katmai board support. The biggest change is the support of ECC DIMM modules in the 440SP(e) SPD DDR2 driver. Please note, that still some problems are left with some memory configurations. See the driver for more details. Signed-off-by: Stefan Roese <sr@denx.de>
* [PATCH] PPC4xx: Add 440SP(e) DDR2 SPD DIMM supportStefan Roese2007-02-20-0/+2759
This patch adds support for the DDR2 controller used on the 440SP and 440SPe. It is tested on the Katmai (440SPe) eval board and works fine with the following DIMM modules: - Corsair CM2X512-5400C4 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5/512 (512MByte per DIMM) - Kingston ValueRAM KVR667D2N5K2/2G (1GByte per DIMM) This patch also adds the nice functionality to dynamically create the TLB entries for the SDRAM (tlb.c). So we should never run into such problems with wrong (too short) TLB initialization again on these platforms. Signed-off-by: Stefan Roese <sr@denx.de>
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