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* 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal2009-08-28-0/+131
* 85xx, 86xx: Add common board_add_ram_info()Peter Tyser2009-07-22-41/+98
* fsl_ddr: Fix DDR3 calculation of rank density with 8GB or moreTimur Tabi2009-07-01-1/+1
* fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BITKumar Gala2009-06-12-39/+41
* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-30-46/+754
* fsl-ddr: Fix two bugs in the ddr infrastructureDave Liu2009-03-30-1/+4
* fsl-ddr: Allow system to boot if we have more than 4G of memoryKumar Gala2009-02-16-1/+1
* fsl-ddr: ignore memctl_intlv_ctl setting if only one DDR controllerKumar Gala2009-02-16-0/+4
* fsl-ddr: use the 1T timing as default configurationDave Liu2009-01-23-1/+1
* fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+8
* fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+13
* fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
* fsl ddr skip interleaving if not supported.Ed Swarthout2008-12-03-12/+17
* Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
* Check DDR interleaving modeHaiying Wang2008-10-18-5/+112
* Pass dimm parameters to populate populate controller optionsHaiying Wang2008-10-18-87/+7
* Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-12/+54
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-7/+7
* Coding style cleanup, update CHANGELOGWolfgang Denk2008-09-13-15/+15
* Fix compiler warning in mpc8xxx ddr codeKumar Gala2008-09-07-2/+4
* FSL DDR: Add DDR2 DIMM paramter supportKumar Gala2008-08-27-0/+339
* FSL DDR: Add DDR1 DIMM paramter supportKumar Gala2008-08-27-0/+343
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-0/+2418
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