| Commit message (Expand) | Author | Age | Lines | |
|---|---|---|---|---|
| * | fsl ddr skip interleaving if not supported. | Ed Swarthout | 2008-12-03 | -12/+17 |
| * | Add debug information for DDR controller registers | Haiying Wang | 2008-10-18 | -0/+13 |
| * | Check DDR interleaving mode | Haiying Wang | 2008-10-18 | -5/+112 |
| * | Pass dimm parameters to populate populate controller options | Haiying Wang | 2008-10-18 | -87/+7 |
| * | Make DDR interleaving mode work correctly | Haiying Wang | 2008-10-18 | -12/+54 |
| * | rename CFG_ macros to CONFIG_SYS | Jean-Christophe PLAGNIOL-VILLARD | 2008-10-18 | -7/+7 |
| * | Coding style cleanup, update CHANGELOG | Wolfgang Denk | 2008-09-13 | -15/+15 |
| * | Fix compiler warning in mpc8xxx ddr code | Kumar Gala | 2008-09-07 | -2/+4 |
| * | FSL DDR: Add DDR2 DIMM paramter support | Kumar Gala | 2008-08-27 | -0/+339 |
| * | FSL DDR: Add DDR1 DIMM paramter support | Kumar Gala | 2008-08-27 | -0/+343 |
| * | FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code. | Kumar Gala | 2008-08-27 | -0/+2418 |
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| U-boot NXP imx6 | git@iatec.biz |
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