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path: root/cpu/mpc8xxx/ddr/ctrl_regs.c
Commit message (Expand)AuthorAgeLines
* fsl-ddr: Fix handling of >4G of memory when !CONFIG_PHYS_64BITKumar Gala2009-06-12-2/+1
* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-30-36/+344
* fsl-ddr: Fix two bugs in the ddr infrastructureDave Liu2009-03-30-1/+4
* fsl-ddr: make the self refresh idle threshold configurableDave Liu2009-01-23-4/+8
* fsl-ddr: clean up the ddr code for DDR3 controllerDave Liu2009-01-23-11/+13
* fsl-ddr: update the bit mask for DDR3 controllerDave Liu2009-01-23-4/+8
* Add debug information for DDR controller registersHaiying Wang2008-10-18-0/+13
* Make DDR interleaving mode work correctlyHaiying Wang2008-10-18-12/+49
* Fix compiler warning in mpc8xxx ddr codeKumar Gala2008-09-07-2/+4
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-0/+993