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* mpc8641: Support 36-bit physical addressingBecky Bruce2008-11-10-11/+33
| | | | | | | | | | | | | | | | | | This patch creates a memory map with all the devices in 36-bit physical space, in addition to the 32-bit map. The CCSR relocation is moved (again, sorry) to allow for the physical address to be 36 bits - this requires translation to be enabled. With 36-bit physical addressing enabled, we are no longer running with VA=PA translations. This means we have to distinguish between the two in the config file. The existing region name is used to indicate the virtual address, and a _PHYS variety is created to represent the physical address. Large physical addressing is not enabled by default. Set CONFIG_PHYS_64BIT in the config file to turn this on. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc8641: Change 32-bit memory mapBecky Bruce2008-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash. The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware. In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file. Documentation has been changed to reflect the new map, as this change is user visible, and affects the OS which runs post-uboot. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLYBecky Bruce2008-11-10-10/+10
| | | | | | | | | | | We define CONFIG_MONITOR_BASE_EARLY to define the initial location of the bootpage in flash. Use this to create an early mapping definition for the FLASH, and change the early_bats code to use this. This change facilitates the relocation of the flash since the early mappings are no longer tied to the final location of the flash. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc86xx: Use SRR0/1/rfi to enable address translation, not blrBecky Bruce2008-11-10-11/+8
| | | | | | | | | | Using a mtmsr/blr means that you have to be executing at the same virtual address once you enable translation. This is unnecessarily restrictive, and is not really how this is usually done. Change it to use the more common mtspr SRR0/SRR1 and rfi method. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc86xx: Move setup_bats into cpu_init_fBecky Bruce2008-11-10-5/+4
| | | | | | | | | | | In order to later allow for a physical relocation of the flash, setup_bats, which sets up the final BAT mapping for the board, needs to happen *after* init_laws(). Otherwise, there will be no window programmed for the flash at the new physical location at the point when we change the mmu translation. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* powerpc: change 86xx SMP boot methodBecky Bruce2008-11-04-73/+277
| | | | | | | | | We put the bootpg for the secondary cpus into memory and use BPTR to get to it. This is a step towards converting to the ePAPR boot methodology. Also, the code is written to deal properly with more than 4GB of RAM. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* powerpc 86xx: Handle CCSR relocation earlierBecky Bruce2008-11-03-5/+24
| | | | | | | | | | | | | | | Currently, the CCSR gets relocated while translation is enabled, meaning we need 2 BAT translations to get to both the old location and the new location. Also, the DEFAULT CCSR location has a dependency on the BAT that maps the FLASH region. Moving the relocation removes this unnecessary dependency. This makes it easier and more intutive to modify the board's memory map. Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same BAT for CCSR space. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* 86xx: remove the redundant r2 global data pointer saveDave Liu2008-10-30-1/+0
| | | | | | | | | | The commit 67256678f00c09b0a7f19e862e5c1847553d31bc add the another global data pointer save, but in fact the global data pointer will be initialized in the board_init_r, so remove it such as the 85xx/83xx family. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
* 86xx: remove the unused code for 86xx familyDave Liu2008-10-30-14/+0
| | | | | | | | I believe these code was copied from 74xx family, but for 86xx, it is unused. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
* 86xx: Move the clear_tlbs before MMU turn onDave Liu2008-10-30-1/+4
| | | | | | | | | | We must invalidate TLBs before MMU turn on, but currently the code is not, if there are some stale TLB entry valid in the TLBs, it will cause strange issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-120/+120
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* 74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx versionKumar Gala2008-10-18-5/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheNick Spence2008-10-13-4/+4
| | | | | | | | | | This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com>
* 86xx: remove redudant code with lib_ppc/interrupts.cKumar Gala2008-10-13-124/+7
| | | | | | | | | | For some reason we duplicated the majority of code in lib_ppc/interrupts.c Not know how that happened, but there is no good reason for it. Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Pass in tsec_info struct through tsec_initializeAndy Fleming2008-09-02-19/+7
| | | | | | | | | | | | | The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.Kumar Gala2008-08-28-1/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Remove old SPD support from cpu/mpc86xxKumar Gala2008-08-27-1352/+0
| | | | | | | All 86xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add 86xx specific register settingKumar Gala2008-08-27-0/+92
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: rework fdt_fixup_ethernet() to use env instead of bd_tKumar Gala2008-08-21-1/+1
| | | | | | | | | | Move to using the environment variables 'ethaddr', 'eth1addr', etc.. instead of bd->bi_enetaddr, bi_enet1addr, etc. This makes the code a bit more flexible to the number of ethernet interfaces. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Clean up usage of icache_disable/dcache_disableKumar Gala2008-08-19-0/+4
| | | | | | | | | | | | There is no point in disabling the icache on 7xx/74xx/86xx parts and not also flushing the icache. All callers of invalidate_l1_instruction_cache() call icache_disable() right after. Make it so icache_disable() calls invalidate_l1_instruction_cache() for us. Also, dcache_disable() already calls dcache_flush() so there is no point in the explicit calls of dcache_flush(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* POWERPC 86xx: Move BAT setup code to CBecky Bruce2008-08-11-119/+25
| | | | | | | | | | This is needed because we will be possibly be locating devices at physical addresses above 32bits, and the asm preprocessing does not appear to deal with ULL constants properly. We now call write_bat in lib_ppc/bat_rw.c. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
* 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreqPaul Gortmaker2008-07-14-1/+1
| | | | | | | | | | Some boards that have external 16550 UARTs don't have a direct tie between bi_busfreq and the clock used for the UARTs. Boards that do have such a tie should set CFG_NS16550_CLK to be get_bus_freq(0) -- which most of them do already. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* Fix some more print() format errors.Wolfgang Denk2008-07-11-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge commit 'wd/master'Jon Loeliger2008-07-10-0/+26
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| * Minor coding style cleanup; update CHANGELOGWolfgang Denk2008-07-10-2/+1
| | | | | | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
| * Add mechanisms for CPU and board-specific Ethernet initializationBen Warren2008-07-06-0/+27
| | | | | | | | | | | | | | | | This patch is the first step in cleaning up net/eth.c, by moving Ethernet initialization to CPU or board-specific code. Initial implementation is only on the Freescale TSEC controller, but others will be added soon. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Feed the watchdog in u-boot for 8610 board.Jason Jin2008-07-07-0/+15
|/ | | | | | | | | The watchdog on 8610 board is enabled by setting sw[6] to on. Once enabled, the watchdog can not be disabled by software. So feed the dog in u-boot is necessary for normal operation. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc85xxWolfgang Denk2008-06-11-6/+3
|\ | | | | | | | | | | | | | | Conflicts: include/asm-ppc/fsl_lbc.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| * 85xx/86xx: Move to dynamic mgmt of LAWsKumar Gala2008-06-11-6/+3
| | | | | | | | | | | | | | | | | | | | | | With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* | MPC86xx: Change traps.c to not reference non-addressable memoryBecky Bruce2008-06-06-1/+7
|/ | | | | | | | | | | | Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd to prevent us from trying to access non-mapped memory. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* PPC: 86xx Add bat registers to reginfo commandBecky Bruce2008-06-03-1/+3
| | | | Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Big white-space cleanup.Wolfgang Denk2008-05-21-8/+8
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* 7450 and 86xx L2 cache invalidate bug correctionsWheatley Travis2008-05-09-1/+1
| | | | | | | | | | | | | | The 7610 and related parts have an L2IP bit in the L2CR that is monitored to signal when the L2 cache invalidate is complete whereas the 7450 and related parts utilize L2I for this purpose. However, the current code does not account for this difference. Additionally the 86xx L2 cache invalidate code used an "andi" instruction where an "andis" instruction should have been used. This patch addresses both of these bugs. Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com> Acked-By: Jon Loeliger <jdl@freescale.com>
* Fix calculation of I2C clock for some 86xx chipsTimur Tabi2008-04-30-1/+13
| | | | | | | | | Some 86xx chips use CCB as the base clock for the I2C, and others used CCB/2. There is no pattern that can be used to determine which chips use which frequency, so the only way to determine is to look up the actual SOC designation and use the right value for that SOC. Signed-off-by: Timur Tabi <timur@freescale.com>
* 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docsKumar Gala2008-04-29-2/+2
| | | | | | | All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update SVR numbers to expand supportAndy Fleming2008-03-26-1/+1
| | | | | | | | | | | | | FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 86xx: Convert sbc8641d to use libfdt.Jon Loeliger2008-02-18-66/+47
| | | | | | | | | | | | | | | This is the proper fix for a missing closing brace in the function ft_cpu_setup() noticed by joe.hamman <at> embeddedspecialties.com. The ft_cpu_setup() function in mpc8641hpcn.c should have been removed earlier as it was under the obsolete CONFIG_OF_FLAT_TREE, but was missed. Only, the sbc8641d was nominally still using it. It all got ripped out, and the funcality that was in ft_board_setup() was refactored to remove the CPU portions into the new file cpu/mpc86xx/fdt.c instead. Make sbc8641d use this now. Based loosely on an original patch from joe.hamman@embeddedspecialties.com Signed-off-by: Jon Loeliger <jdl@freescale.com>
* mpc86xx: Fix unused variable 'config' and 'immap'Jean-Christophe PLAGNIOL-VILLARD2008-02-18-4/+6
| | | | | | and remove useless CONFIG_DDR_INTERLEAVE Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* mpc86xx: Fix implicit declaration of functions 'init_laws' and 'disable_law'Jean-Christophe PLAGNIOL-VILLARD2008-02-18-0/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-mpc86xxWolfgang Denk2008-02-15-79/+108
|\ | | | | | | | | | | | | | | Conflicts: common/cmd_reginfo.c Signed-off-by: Wolfgang Denk <wd@denx.de>
| * 86xx: Add reginfo commandBecky Bruce2008-01-24-1/+23
| | | | | | | | Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * 86xx: Remove old-style law setup codeBecky Bruce2008-01-24-32/+0
| | | | | | | | | | | | This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * 86xx: Support new law setup method and convert mpc8641Becky Bruce2008-01-24-1/+24
| | | | | | | | | | | | | | | | Adds the support code in cpu/mpc86xx for the new law setup code recently created fsl_law.c, and changes the MPC8641HPCN config to use this code. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
| * 86xx: Rearrange the sequence in start.SBecky Bruce2008-01-24-53/+69
| | | | | | | | | | | | | | | | | | | | | | | | * split the BAT initialization so that only 2 BATs (for the boot page and stack) are programmed very early on. The rest are initialized later. * Move other BAT setup, ccsrbar setup, and law setup later in the code after translation has been enabled. These changes will facilitate the moving of law and BAT initialization to C code, and will aid with 36-bit physical addressing support. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* | 85xx, 86xx: Determine I2C clock frequencies and store in global_dataTimur Tabi2008-02-14-0/+2
| | | | | | | | | | | | | | | | | | Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx. Update the get_clocks() function in 85xx and 86xx to determine the I2C clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk. Signed-off-by: Timur Tabi <timur@freescale.com>
* | PPC: Use r2 instead of r29 as global data pointerWolfgang Denk2008-02-14-2/+2
| | | | | | | | | | | | | | | | | | | | | | | | R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc will refuse to use load/store multiple insns; instead, it issues a list of simple load/store instructions upon function entry and exit, resulting in bigger code size, which in turn makes the build for a few boards fail. Use r2 instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
* | ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-44/+0
|/ | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* 86xx: Support 2GB DIMMsBecky Bruce2008-01-10-1/+10
| | | | | | | | Configure the number of bits used to address the banks inside the SDRAM device. The default register value of 0 means 2 bits to address 4 banks. Higher capacity devices like a 2GB DIMM require 3 bits to address 8 banks. Signed-off-by: Becky Bruce <bgill@freescale.com>
* Merge commit 'remotes/wd/master'Jon Loeliger2007-11-20-1/+6
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