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* ppc/85xx/86xx: Bug fix: call to puts in probecpu() moved to checkcpu().Poonam Aggrwal2009-09-08-0/+6
| | | | | | | While in probecpu() UART is still not initialized. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx/86xx: Device tree fixup for number of coresPoonam Aggrwal2009-09-08-0/+3
| | | | | | | | | | | | | | Fixing the number of cores in the device tree based on the actual number of cores on the system. With this same device tree image can be used for dual core and single core members of otherwise exactly same SOC. For example: * P2020RDB and P2010RDB * P1020RDB and P1011RDB * MPC8641D and MPC8641 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal2009-09-08-4/+1
| | | | | | | | | | | Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal2009-08-28-6/+8
| | | | | | | | | | | | | The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal2009-08-28-31/+1
| | | | | | | | Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c and moved to cpu/mpc8xxx/cpu.c(new file) Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 86xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala2009-08-28-1/+2
| | | | | | | | | | | | For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_MPC86xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8641=1 However these are all captured in the config.h and thus redudant. Also moved common 86xx flags into cpu/mpc86xx/config.mk. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 86xx: Rename ccsr_ddr's sdram_mode_1, sdram_cfg_1 fieldsPeter Tyser2009-07-22-2/+2
| | | | | | | | Rename sdram_mode_1 to sdram_mode and sdram_cfg_1 to sdram_cfg to match the 86xx user's manual and other Freescale architectures Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Move dma_init() call to common codePeter Tyser2009-07-01-0/+3
| | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Break out DMA code to a common filePeter Tyser2009-07-01-55/+0
| | | | | | | | DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 86xx: Add CPU_TYPE_ENTRY supportKumar Gala2009-06-30-12/+21
| | | | | | | | Unify with 83xx and 85xx and use CPU_TYPE_ENTRY. We are going to use this to convey the # of cores and DDR width in the near future so its good to keep in sync. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl/85xx, 86xx: Sync up DMA codePeter Tyser2009-06-12-6/+8
| | | | | | | | | | | | | | | | | | | | | The following changes were made to sync up the DMA code between the 85xx and 86xx architectures which will make it easier to break out common 8xxx DMA code: 85xx: - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits only have an affect when the SBPATMU bit is set. - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA status register. We may as well clear all 32 bits of the register... 86xx: - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers - Add clearing of errors in the DMA status register when initializing the controller - Clear the channel start bit in the DMA mode register after a transfer Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Create common fsl_dma.h for 85xx and 86xx cpusPeter Tyser2009-06-12-12/+15
| | | | | | | | Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Replace __attribute references with __attribute__Peter Tyser2009-04-28-1/+1
| | | | | | | | __attribute__ follows gcc's documented syntax and is generally more common than __attribute. This change is only asthetic and should not affect functionality. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 86xx: Cleanup MP supportKumar Gala2009-04-01-52/+49
| | | | | | | | | | | | | | * Use CONFIG_MP instead of CONFIG_NUM_CPUS to match 85xx * Introduce determine_mp_bootpg() helper. We'll need this to address a bug introduced in v2009.03 with 86xx MP booting. We have to make sure to reserve the region of memory used for the MP bootpg() so other u-boot code doesn't use it. * Added dummy versions of cpu_reset(), cpu_status() & cpu_release() to allow cmd_mp.c to build and work. In the future we should look at implementing all these functions. This could be common w/85xx if we use spin tables on 86xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 86xx: Update CPU info output on bootupPeter Tyser2009-02-16-41/+41
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | - Update style of 86xx CPU information on boot to more closely match 85xx boards - Fix detection of 8641/8641D - Use strmhz() to display frequencies - Display L1 information - Display L2 cache size - Fixed CPU/SVR version output == Before == Freescale PowerPC CPU: Core: E600 Core 0, Version: 0.2, (0x80040202) System: Unknown, Version: 2.1, (0x80900121) Clocks: CPU:1066 MHz, MPX: 533 MHz, DDR: 266 MHz, LBC: 133 MHz L2: Enabled Board: X-ES XPedite5170 3U VPX SBC == After == CPU: 8641D, Version: 2.1, (0x80900121) Core: E600 Core 0, Version: 2.2, (0x80040202) Clock Configuration: CPU:1066.667 MHz, MPX:533.333 MHz DDR:266.667 MHz (533.333 MT/s data rate), LBC:133.333 MHz L1: D-cache 32 KB enabled I-cache 32 KB enabled L2: 512 KB enabled Board: X-ES XPedite5170 3U VPX SBC Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 86xx: Reset updatePeter Tyser2009-02-16-61/+19
| | | | | | | | | | Update the 86xx reset sequence to try executing a board-specific reset function. If the board-specific reset is not implemented or does not succeed, then assert #HRESET_REQ. Using #HRESET_REQ is a more standard reset procedure than the previous method and allows all board peripherals to be reset if needed. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* mpc86xx: Add support to populate addr map based on BATsBecky Bruce2009-02-10-0/+27
| | | | | | | If CONFIG_ADDR_MAP is enabled, update the address map whenever we write a bat. Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org>
* MPC86xx: fix build warningsWolfgang Denk2009-01-12-3/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho2008-12-19-18/+23
| | | | | | | | | | | | | | | | | | | | | | | Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* mpc86xx: Double local bus clock dividerTrent Piepho2008-12-19-0/+1
| | | | | | | | The local bus clock divider should be doubled for both 8610 and 8641. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-1/+1
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* mpc8[56]xx: Put localbus clock in device treeTrent Piepho2008-12-19-0/+9
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the localbus frequency in the device tree, the same way the CPU, TB, CCB, and various other frequencies are exported in their respective device tree nodes. Some localbus devices need this information to be programed correctly, so it makes sense to export it along with the other frequencies. Unfortunately, when someone wrote the localbus dts bindings, they didn't bother to define what the "compatible" property should be. So it seems no one was quite sure what to put in their dts files. Based on current existing dts files in the kernel source, I've used "fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all of the 85xx devices, and are looked for by the Linux code. The eLBC is apparently not entirely backward compatible with the pq3 LBC and so eLBC equipped platforms like 8572 won't use pq3-localbus. For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems and is also looked for by the Linux code. On MPC8641, I've also used "fsl,mpc8641-localbus" as it is also commonly used in dts files, some of which don't use "fsl,elbc" or any other acceptable name to match on. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* Coding style cleanup, update CHANGELOG.Wolfgang Denk2008-12-16-2/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fix new found CFG_Jean-Christophe PLAGNIOL-VILLARD2008-12-14-1/+1
| | | | | | | Also fix some minor typos. Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com> Signed-off-by: Wolfgang Denk <wd@denx.de>
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-1/+2
| | | | | | | Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* mpc8641: Support 36-bit physical addressingBecky Bruce2008-11-10-11/+33
| | | | | | | | | | | | | | | | | | This patch creates a memory map with all the devices in 36-bit physical space, in addition to the 32-bit map. The CCSR relocation is moved (again, sorry) to allow for the physical address to be 36 bits - this requires translation to be enabled. With 36-bit physical addressing enabled, we are no longer running with VA=PA translations. This means we have to distinguish between the two in the config file. The existing region name is used to indicate the virtual address, and a _PHYS variety is created to represent the physical address. Large physical addressing is not enabled by default. Set CONFIG_PHYS_64BIT in the config file to turn this on. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc8641: Change 32-bit memory mapBecky Bruce2008-11-10-1/+1
| | | | | | | | | | | | | | | | | | | | | | The memory map on the 8641hpcn is modified to look more like the 85xx boards; this is a step towards a more standardized layout going forward. As part of this change, we now relocate the flash. The regions for some of the mappings were far larger than they needed to be. I have reduced the mappings to match the actual sizes supported by the hardware. In addition I have removed the comments at the head of the BAT blocks in the config file, rather than updating them. These get horribly out of date, and it's a simple matter to look at the defines to see what they are set to since everything is right here in the same file. Documentation has been changed to reflect the new map, as this change is user visible, and affects the OS which runs post-uboot. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc86xx: Change early FLASH mapping to 1M at CONFIG_MONITOR_BASE_EARLYBecky Bruce2008-11-10-10/+10
| | | | | | | | | | | We define CONFIG_MONITOR_BASE_EARLY to define the initial location of the bootpage in flash. Use this to create an early mapping definition for the FLASH, and change the early_bats code to use this. This change facilitates the relocation of the flash since the early mappings are no longer tied to the final location of the flash. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc86xx: Use SRR0/1/rfi to enable address translation, not blrBecky Bruce2008-11-10-11/+8
| | | | | | | | | | Using a mtmsr/blr means that you have to be executing at the same virtual address once you enable translation. This is unnecessarily restrictive, and is not really how this is usually done. Change it to use the more common mtspr SRR0/SRR1 and rfi method. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* mpc86xx: Move setup_bats into cpu_init_fBecky Bruce2008-11-10-5/+4
| | | | | | | | | | | In order to later allow for a physical relocation of the flash, setup_bats, which sets up the final BAT mapping for the board, needs to happen *after* init_laws(). Otherwise, there will be no window programmed for the flash at the new physical location at the point when we change the mmu translation. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* powerpc: change 86xx SMP boot methodBecky Bruce2008-11-04-73/+277
| | | | | | | | | We put the bootpg for the secondary cpus into memory and use BPTR to get to it. This is a step towards converting to the ePAPR boot methodology. Also, the code is written to deal properly with more than 4GB of RAM. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* powerpc 86xx: Handle CCSR relocation earlierBecky Bruce2008-11-03-5/+24
| | | | | | | | | | | | | | | Currently, the CCSR gets relocated while translation is enabled, meaning we need 2 BAT translations to get to both the old location and the new location. Also, the DEFAULT CCSR location has a dependency on the BAT that maps the FLASH region. Moving the relocation removes this unnecessary dependency. This makes it easier and more intutive to modify the board's memory map. Swap BATs 3 and 4 on 8610 so that all 86xx boards use the same BAT for CCSR space. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* 86xx: remove the redundant r2 global data pointer saveDave Liu2008-10-30-1/+0
| | | | | | | | | | The commit 67256678f00c09b0a7f19e862e5c1847553d31bc add the another global data pointer save, but in fact the global data pointer will be initialized in the board_init_r, so remove it such as the 85xx/83xx family. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
* 86xx: remove the unused code for 86xx familyDave Liu2008-10-30-14/+0
| | | | | | | | I believe these code was copied from 74xx family, but for 86xx, it is unused. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Kumar Gala <kumar.gala@freescale.com>
* 86xx: Move the clear_tlbs before MMU turn onDave Liu2008-10-30-1/+4
| | | | | | | | | | We must invalidate TLBs before MMU turn on, but currently the code is not, if there are some stale TLB entry valid in the TLBs, it will cause strange issue. Signed-off-by: Dave Liu <daveliu@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-120/+120
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* 74xx/7xx/86xx: Rename flush_data_cache to flush_dcache to match 85xx versionKumar Gala2008-10-18-5/+5
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc86xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cacheNick Spence2008-10-13-4/+4
| | | | | | | | | | This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence@freescale.com>
* 86xx: remove redudant code with lib_ppc/interrupts.cKumar Gala2008-10-13-124/+7
| | | | | | | | | | For some reason we duplicated the majority of code in lib_ppc/interrupts.c Not know how that happened, but there is no good reason for it. Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Pass in tsec_info struct through tsec_initializeAndy Fleming2008-09-02-19/+7
| | | | | | | | | | | | | The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* FSL DDR: Remove duplicate setting of cs0_bnds register on 86xx.Kumar Gala2008-08-28-1/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Remove old SPD support from cpu/mpc86xxKumar Gala2008-08-27-1352/+0
| | | | | | | All 86xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add 86xx specific register settingKumar Gala2008-08-27-0/+92
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-1/+4
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: rework fdt_fixup_ethernet() to use env instead of bd_tKumar Gala2008-08-21-1/+1
| | | | | | | | | | Move to using the environment variables 'ethaddr', 'eth1addr', etc.. instead of bd->bi_enetaddr, bi_enet1addr, etc. This makes the code a bit more flexible to the number of ethernet interfaces. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Clean up usage of icache_disable/dcache_disableKumar Gala2008-08-19-0/+4
| | | | | | | | | | | | There is no point in disabling the icache on 7xx/74xx/86xx parts and not also flushing the icache. All callers of invalidate_l1_instruction_cache() call icache_disable() right after. Make it so icache_disable() calls invalidate_l1_instruction_cache() for us. Also, dcache_disable() already calls dcache_flush() so there is no point in the explicit calls of dcache_flush(). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* POWERPC 86xx: Move BAT setup code to CBecky Bruce2008-08-11-119/+25
| | | | | | | | | | This is needed because we will be possibly be locating devices at physical addresses above 32bits, and the asm preprocessing does not appear to deal with ULL constants properly. We now call write_bat in lib_ppc/bat_rw.c. Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com>
* 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreqPaul Gortmaker2008-07-14-1/+1
| | | | | | | | | | Some boards that have external 16550 UARTs don't have a direct tie between bi_busfreq and the clock used for the UARTs. Boards that do have such a tie should set CFG_NS16550_CLK to be get_bus_freq(0) -- which most of them do already. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
* Fix some more print() format errors.Wolfgang Denk2008-07-11-1/+1
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge commit 'wd/master'Jon Loeliger2008-07-10-0/+26
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