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path: root/cpu/mpc86xx/spd_sdram.c
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* 86xx: Remove old-style law setup codeBecky Bruce2008-01-24-27/+0
| | | | | | This includes mpc8610hpcd, mpc8641hpcn, and sbc8641d. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* 86xx: Support new law setup method and convert mpc8641Becky Bruce2008-01-24-1/+15
| | | | | | | | Adds the support code in cpu/mpc86xx for the new law setup code recently created fsl_law.c, and changes the MPC8641HPCN config to use this code. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* 86xx: Support 2GB DIMMsBecky Bruce2008-01-10-1/+10
| | | | | | | | Configure the number of bits used to address the banks inside the SDRAM device. The default register value of 0 means 2 bits to address 4 banks. Higher capacity devices like a 2GB DIMM require 3 bits to address 8 banks. Signed-off-by: Becky Bruce <bgill@freescale.com>
* Fix compiler warnings for PPC systems. Update CHANGELOG.Wolfgang Denk2007-11-18-1/+3
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 86xx: Fix broken variable reference when #def DEBUGing.Jon Loeliger2007-11-17-2/+4
| | | | | | Sometimes you can't reference the DDR2 controller variables. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* 86xx: Allow for fewer DDR slots per memory controller.Jon Loeliger2007-10-16-9/+21
| | | | | | | | | | | | | As a direct correlation exists between DDR DIMM slots and SPD EEPROM addresses used to configure them, use the individually defined SPD_EEPROM_ADDRESS* values to determine if a DDR DIMM slot should have its SPD configuration read or not. Effectively, this now allows for 1 or 2 DIMM slots per memory controller. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Rewrote picos_to_clk() to avoid rounding errors.James Yang2007-05-01-8/+20
| | | | | | | | Clarified that conversion is to DRAM clocks rather than platform clocks. Made function static to spd_sdram.c. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Add support for 8641 Rev 2 silicon.Ed Swarthout2007-03-22-2/+2
| | | | | | | | Without this patch, I am unable to get to the prompt on rev 2 silicon. Only set ddrioovcr for rev1. Signed-off-by: Ed Swarthout<ed.swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com>
* MPC86xx: Cleaned up unused and conditionally used local variables.Jon Loeliger2006-10-27-6/+2
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Coding style changes to remove local varible blocksJon Loeliger2006-10-10-74/+64
| | | | and reformat a bit nicer.
* Fix missing tCycle/modfreq calculation.John Traill2006-09-29-0/+2
| | | | Signed-off-by: John Traill <john.traill@freescale.com>
* Remove bogus msync and use volatile asm.Jon Loeliger2006-08-29-3/+3
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* Fix caslat calculationJohn Traill2006-08-09-96/+39
| | | | Signed-off-by: John Traill <john.traill@freescale.com>
* Fix two SDRAM setup bugs.Haiying Wang2006-05-30-7/+7
| | | | | | | Fix ECC setup bug. Enable 1T/2T based on number of DIMMs present. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Enable dual DDR controllers and interleaving.Jon Loeliger2006-05-19-121/+494
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* Cleanup whitespaces and style issues.Jon Loeliger2006-04-27-5/+4
| | | | | | | Removed //-style comments. Use 80-column lines. Remove trailing whitespace. Remove dead code and debug cruft.
* Initial support for MPC8641 HPCN board.Jon Loeliger2006-04-26-0/+1017
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