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* 85xx: Set HID1[mbdd] on e500v2 rev5.0 or greaterSandeep Gopalpet2010-04-07-0/+14
| | | | | | | The HID1[MBDD] bit is new on rev5.0 or greater cores and will optimize the performance of mbar/eieio instructions. Signed-off-by: Sandeep Gopalpet <sandeep.kumar@freescale.com>
* 85xx: Added various P1012/P1013/P1021/P1022 definesKumar Gala2010-04-07-0/+4
| | | | | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added P1012/P1013/P1021/P1022 to cpu_type_list and SVR list * Added number of LAWs for P1012/P1013/P1021/P1022 * Set CONFIG_MAX_CPUS to 2 for P1021/P1022 * PCI port config Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add defines for BUCSR bits to make code more readableKumar Gala2010-04-07-5/+7
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix enabling of L1 cache parity on secondary coresKumar Gala2010-03-30-13/+63
| | | | | | | | | | | Use the same code between primary and secondary cores to init the L1 cache. We were not enabling cache parity on the secondary cores. Also, reworked the L1 cache init code to match the e500mc L2 init code that first invalidates the cache and locks. Than enables the cache and makes sure its enabled before continuing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* kgdb: cpu/mpc* cpu/74xx: include kgdb.h when neededMike Frysinger2010-02-08-0/+1
| | | | | | | | Commit cbb0cab1d929839d broke some platforms which used kgdb code but didn't actually include kgdb.h. So include kgdb.h in all the relevant traps code. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* 85xx: Add support for 'cpu disable' commandKumar Gala2010-01-26-2/+26
| | | | | | Support disabling of a core via user command 'cpu disable'. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add support to disable cpu's in multicore processorsKumar Gala2010-01-26-1/+7
| | | | | | | | | | | Add a disable sub-command to the cpu command that allows for disabling cores in multicore processors. This can be useful for systems that are using multicore chips but aren't utilizing all the cores as a way to reduce power and possibly improve performance. Also updated an added missing copyright. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2010-01-26-9/+32
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| * qe: fixup the snum for MPC8569 Rev2.0Liu Yu2010-01-25-0/+18
| | | | | | | | | | | | | | | | Since 1.0 and 2.0 use different snum table, we fixup the snum value according to SPRN_SVR. Signed-off-by: Liu Yu <yu.liu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Fix the local bus divider mappingDave Liu2010-01-25-1/+6
| | | | | | | | | | | | | | | | The real clock divider is 4 times of the bits LCRR[CLKDIV], according the latest RevF RM. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * Revert "ppc/p4080: Fix reporting of PME & FM clock frequencies"Kumar Gala2010-01-25-6/+6
| | | | | | | | | | | | | | | | | | This reverts commit bc20f9a9527afe8ae406a74f74765d4323f04922. The original code was correct. I clearly need glasses or a brown paper bag. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/p4080: Fix mask width of RCW fields MEM_PLL_RAT, SYS_PLL_RATJames Yang2010-01-25-2/+2
| | | | | | | | | | | | | | | | The masks for MEM_PLL_RAT and SYS_PLL_RAT should have been 5-bits instead of 4. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc: remove -ffixed-r14 gcc option.Joakim Tjernlund2010-01-26-1/+1
| | | | | | | | | | | | This is no loger needed, free up r14 for general usage. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* | ppc: Use r12 instead of r14 as GOT pointer.Joakim Tjernlund2010-01-26-5/+6
| | | | | | | | | | | | | | | | r14 is not supposed to be clobbered by functions. Switch to r12 and call GET_GOT when needed. This will allow u-boot to loose the -ffixed-r14 gcc option. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* | ppc: Loose GOT access in IRQJoakim Tjernlund2010-01-26-30/+3
|/ | | | | | | | Using the GOT in IRQ handlers requires r14 to be -ffixed-r14. Avoid this by relocatate transfer_to_handler too. This will allow to free up r14 later on. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* kgdb: drop duplicate debugger_exception_handlerMike Frysinger2010-01-18-4/+0
| | | | | | | The debugger_exception_handler definition is the same for everyone, so use the common one now. Signed-off-by: Mike Frysinger <vapier@gentoo.org>
* ppc/p4080: Fix reporting of PME & FM clock frequenciesKumar Gala2010-01-05-6/+6
| | | | | | | We incorrectly had the sense of PME_CLK_SEL, FM1_CLK_SEL, FM2_CLK_SEL backwards so we report the wrong frequency. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Map boot page guarded for MP bootKumar Gala2010-01-05-3/+3
| | | | | | | We already map the page cache-inhibited. There is no reason we shouldn't also be marking it guarded to prevent speculative accesses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* p4080: add readback to bootpage translation windowDave Liu2010-01-05-0/+3
| | | | | | | | | We need to add the readback to bootpage translation LAW to make it effect. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Becky Bruce <beckyb@kernel.crashing.org> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocationKumar Gala2010-01-05-6/+6
| | | | | | | | Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Add tracking of TLB CAM usageKumar Gala2010-01-05-0/+65
| | | | | | | | | We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support to set DPAA (data path) devices clock frequenciesKumar Gala2010-01-05-0/+36
| | | | | | Set clock-frequency for Frame Manager 0/1 and Patter Match Engine on p4080. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for e500mc cache stashingKumar Gala2010-01-05-1/+43
| | | | | | | | | | | | | | The e500mc core supports the ability to stash into the L1 or L2 cache, however we need to uniquely identify the caches with an id. We use the following equation to set the various stash-ids: 32 + coreID*2 + 0(L1) or 1(L2) The 0 (for L1) or 1 (for L2) matches the CT field used be various cache control instructions. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* common: delete CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOULHeiko Schocher2009-12-08-4/+0
| | | | | | | | | There is more and more usage of printing 64bit values, so enable this feature generally, and delete the CONFIG_SYS_64BIT_VSPRINTF and CONFIG_SYS_64BIT_STRTOUL defines. Signed-off-by: Heiko Schocher <hs@denx.de>
* Merge branch 'master' into nextWolfgang Denk2009-11-15-6/+10
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| * ppc/85xx: Fix how we determine the number of CAM entriesKumar Gala2009-11-13-2/+2
| | | | | | | | | | | | | | | | We were incorrectly use the max CAM size as the number of entries in the array for setting up the addrmap. We should be using the NENTRY field which is the low 12-bits of TLB1CFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * ppc/85xx: Fix misc L2 cache enabling bugDave Liu2009-10-31-4/+8
| | | | | | | | | | | | | | We need loop-check the flash clear lock and enable bit for L2 cache. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* | ppc/85xx: make boot from NAND full relocation to RAMMingkai Hu2009-11-13-1/+0
|/ | | | | | | | Take advantage of the latest full relocation commit of PPC platform for boot from NAND. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* Coding Style cleanup; update CHANGELOG, prepare -rc1v2009.11-rc1Wolfgang Denk2009-10-28-29/+29
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* mpc85xx: Add eSDHC support for MPC8569E-MDS boardsAnton Vorontsov2009-10-27-0/+4
| | | | | | | | | | | | | | | | | | eSDHC is mutually exlusive with UART0 (in 4-bits mode) and I2C2 (in 1-bit mode). When eSDHC is used, we should switch u-boot console to UART1, and make the proper device-tree fixups. Because of an erratum in prototype boards it is impossible to use eSDHC without disabling UART0 (which makes it quite easy to 'brick' the board by simply issung 'setenv hwconfig esdhc', and not able to interact with U-Boot anylonger). So, but default we assume that the board is a prototype, which is a most safe assumption. There is no way to determine board revision from a register, so we use hwconfig. Signed-off-by: Anton Vorontsov <avorontsov@ru.mvista.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: MP Boot Page Translation updatePeter Tyser2009-10-27-31/+78
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | This change has 3 goals: - Have secondary cores be released into spin loops at their 'true' address in SDRAM. Previously, secondary cores were put into spin loops in the 0xfffffxxx address range which required that boot page translation was always enabled while cores were in their spin loops. - Allow the TLB window that the primary core uses to access the secondary cores boot page to be placed at any address. Previously, a TLB window at 0xfffff000 was always used to access the seconary cores' boot page. This TLB address requirement overlapped with other peripherals on some boards (eg XPedite5370). By default, the boot page TLB will still use the 0xfffffxxx address range, but this can be overridden on a board-by-board basis by defining a custom CONFIG_BPTR_VIRT_ADDR. Note that the TLB used to map the boot page remains in use while U-Boot executes. Previously it was only temporarily used, then restored to its initial value. - Allow Boot Page Translation to be disabled on bootup. Previously, Boot Page Translation was always left enabled after secondary cores were brought out of reset. This caused the 0xfffffxxx address range to somewhat "magically" be translated to an address in SDRAM. Some boards may not want this oddity in their memory map, so defining CONFIG_MPC8xxx_DISABLE_BPTR will turn off Boot Page Translation after the secondary cores are initialized. These changes are only applicable to 85xx boards with CONFIG_MP defined. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix crashes due to generation of SPE instructionLeon Woestenberg2009-10-26-0/+5
| | | | | | | | | | | | | | | | | | | | | | | | | | U-Boot crashed on the last instruction: int parse_stream_outer(struct in_str *inp, int flag) { effa4784: 94 21 ff 38 stwu r1,-200(r1) effa4788: 7c 08 02 a6 mflr r0 effa478c: 42 9f 00 05 bcl- 20,4*cr7+so,effa4790 <parse_stream_outer+0xc> effa4790: 7d 80 00 26 mfcr r12 effa4794: 13 c1 b3 21 evstdd r30,176(r1) ...which is a SPE instruction, although -mno-spe was used. tmp/cross/ppce500v2/bin/powerpc-angstrom-linux-gnuspe-gcc --version powerpc-angstrom-linux-gnuspe-gcc (GCC) 4.3.3 Seems to be a known issue (since 2008-04?!) Googled some, turns out this patch/workaround works for me on MPC8536DS. See http://gcc.gnu.org/ml/gcc-patches/2008-04/msg00311.html for more info Signed-off-by: Leon Woestenberg <leon@sidebranch.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Make L2 support more robustDave Liu2009-10-26-1/+4
| | | | | | | According the user manual, we need loop-check the L2 enable bit set. Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* relocation: Do not relocate NULL pointers.Joakim Tjernlund2009-10-08-2/+4
| | | | | | | | | | NULL is an absolute value and should not be relocated. After this correction code like: void weak_fun(void) __attribute__((weak)); printf("weak_fun:%p\n", weak_fun); will still print null after relocation. Signed-off-by: Joakim Tjernlund <Joakim.Tjernlund@transmode.se>
* 85xx: Ensure BSS segment isn't linked at address 0Peter Tyser2009-10-08-0/+11
| | | | | | | | | | | | | | | | When U-Boot is relocated from flash to RAM pointers are modified accordingly. However, pointers initialzed with NULL values should not be modified so that they maintain their intended NULL value. If the BSS segment is linked at address 0 its address will not be updated as necessary during relocation. This is a temporary workaround. The end goal is to add support to U-Boot to dynamically locate the BSS at an arbitrary address at runtime. When the ability to fixup the BSS inteligently is added, this workaround can be removed and the 85xx link script can put the BSS at a fixed address at link time. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc: Enable full relocation to RAMPeter Tyser2009-10-03-1/+0
| | | | | | | | | | | | | The following changes allow U-Boot to fully relocate from flash to RAM: - Remove linker scripts' .fixup sections from the .text section - Add -mrelocatable to PLATFORM_RELFLAGS for all boards - Define CONFIG_RELOC_FIXUP_WORKS for all boards Previously, U-Boot would partially relocate, but statically initialized pointers needed to be manually relocated. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc/p4080: Determine various chip frequencies on CoreNet platformsKumar Gala2009-09-24-4/+127
| | | | | | | | | | The means to determine the core, bus, and DDR frequencies are completely new on CoreNet style platforms. Additionally on p4080 we can have different frequencies for FMAN and PME IP blocks. We need to keep track of the FMAN & PME frequencies since they are used for time stamping capabilities inside each block. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Handle timebase enabling and frequency reportingKumar Gala2009-09-24-1/+22
| | | | | | | | | On CoreNet style platforms the timebase frequency is the bus frequency defined by 16 (on PQ3 it is divide by 8). Also on the CoreNet platforms the core not longer controls the enabling of the timebase. We now need to enable the boot core's timebase via CCSR register writes. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: Add various p4080 related defines (and p4040)Kumar Gala2009-09-24-0/+1
| | | | | | | | | | | There are various locations that we have chip specific info: * Makefile for which ddr code to build * Added p4080 & p4040 to cpu_type_list and SVR list * Added number of LAWs for p4080 * Set CONFIG_MAX_CPUS to 8 for p4080 Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: CoreNet platfrom style secondary core releaseKumar Gala2009-09-24-3/+65
| | | | | | | | | The CoreNet platform style of bringing secondary cores out of reset is a bit different that the PQ3 style. Mostly the registers that we use to setup boot translation, enable time bases, and boot release the cores have moved around. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/p4080: CoreNet platfrom style CCSRBAR settingKumar Gala2009-09-24-18/+54
| | | | | | | | On CoreNet based platforms the CCSRBAR address is split between an high & low register and we no longer shift the address. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Scott Wood <scottwood@freescale.com>
* ppc/85xx: Fix enabling of L2 cacheKumar Gala2009-09-24-3/+4
| | | | | | | We need to flash invalidate the locks in addition to the cache before we enable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx-fdt: Fixed l2-ctlr's compatible prop for QorIQVivek Mahajan2009-09-24-3/+10
| | | | | | | | The code assumed names where just numbers and always prefixed 'mpc'. However newer QorIQ don't follow the mpc naming scheme. Signed-off-by: Vivek Mahajan <vivek.mahajan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: add cpu init config file for boot from NANDMingkai Hu2009-09-24-0/+63
| | | | | | | | | When boot from NAND, the NAND flash must be connected to br/or0. Also init RAM(L2 SRAM or DDR SDRAM) for load the second image to it. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: add ld script file for boot from NANDMingkai Hu2009-09-24-0/+67
| | | | | | | | | The first stage 4K image uses a seperate ld script file to generate 4K image. This patch moves it to the cpu/mpc85xx/* to make it avaliable for 85xx platform. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Disable all async interrupt sources when we bootKumar Gala2009-09-15-0/+11
| | | | | | | | We should make sure to clear MSR[ME, CE, DE] when we boot an OS image since we have changed the exception vectors and the OSes vectors might not be setup we should avoid async interrupts at all costs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Split out cpu_init_early into its own file for NAND_SPLKumar Gala2009-09-15-51/+77
| | | | | | | By pulling out cpu_init_early we can build just it and not all of cpu_init for NAND_SPL. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Change cpu_init_early_f so we can use with NAND SPLKumar Gala2009-09-15-9/+25
| | | | | | | Use write_tlb and don't use memset so we can use the same code for cpu_init_early_f between NAND SPL and not. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu2009-09-15-1/+181
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Move code around to prep for NAND_SPLKumar Gala2009-09-15-23/+23
| | | | | | | | If we move some of the functions in tlb.c around we need less ifdefs. The first stage loader just needs invalidate_tlb and init_tlbs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
generated by cgit v1.1 at 2024-11-05 16:04:45 +0000