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* ppc/85xx,86xx: Handling Unknown SOC versionPoonam Aggrwal2009-09-08-7/+3
| | | | | | | | | | | Incase the system is detected with Unknown SVR, let the system boot with a default value and a proper message. Now with dynamic detection of SOC properties from SVR, this is necessary to prevent a crash. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Cleanup makefile and related optional filesKumar Gala2009-09-08-18/+19
| | | | | | | | Cleaned up cpu/mpc85xx/Makefile to use CONFIG_* for those obvious cases we have like PCI, CPM2, QE. Also reworked it to use one line per file for everything and sorted in alphabetical order. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix bug in setup_mp codeKumar Gala2009-09-08-3/+29
| | | | | | | | | | | | | | Its possible that we try and copy the boot page code out of flash into a DDR location that doesn't have a TLB cover it. For example, if we have 3G of DDR we typically only map the first 2G. In the cases of 4G+ this wasn't an issue since the reset page TLB mapping covered the last page of memory which we wanted to copy to. We now change the physical address of the reset page TLB to map to the true physical location of the boot page code, copy and than set the TLB back to its 1:1 mapping of the reset page. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Add a simple function to search the TLBKumar Gala2009-09-08-0/+27
| | | | | | | | | | | Allow us to search the TLB array based on an address. This is useful if we want to change an entry but dont know where it happens to be located. For example, the boot page mapping we use on MP or the flash TLB that we change the WIMGE settings for after we've relocated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for setting IVORs to fixed offset defaultsKumar Gala2009-09-08-0/+95
| | | | | | | | | | | | In future Book-E implementations IVORs will most likely go away and be replaced with fixed offsets. The IVPR will continue to exist to allow for relocation of the interrupt vectors. This code adds support to setup the IVORs as their fixed offset values per the ISA 2.06 spec when we transition from u-boot to another OS either via 'bootm' or a cpu release. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix up eSDHC controller clock frequency in the device treeDipen Dudhat2009-09-08-0/+7
| | | | | Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/8xxx: Remove ddr_pd_cntl register since it doesn't existKumar Gala2009-09-08-1/+0
| | | | | | | | The ddr_pd_cntl isn't defined in any reference manual and thus we wil remove especially since we set it to 0, which would most likely be its POR value. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Use CONFIG_FSL_ESDHC to enable sdhc clkDipen Dudhat2009-09-08-1/+1
| | | | | | | | | | Enable eSDHC Clock based on generic CONFIG_FSL_ESDHC define instead of a platform define. This will enable all the 85xx platforms to use sdhc_clk based on CONFIG_FSL_ESDHC. Signed-off-by: Gao Guanhua <B22826@freescale.com> Signed-off-by: Dipen Dudhat <dipen.dudhat@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Improve MPIC initializationTimur Tabi2009-08-28-5/+7
| | | | | | | | | The MPIC initialization code for Freescale e500 CPUs was not using I/O accessors, and it was not issuing a read-back to the MPIC after setting mixed mode. This may be the cause of a spurious interrupt on some systems. Signed-off-by: Timur Tabi <timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added single core members of FSL P1xx/P2xx processors seriesPoonam Aggrwal2009-08-28-1/+3
| | | | | | | | P1011 - Single core variant of P1020 P2010 - Single core variant of P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add L2SRAM Register's macro definitionMingkai Hu2009-08-28-2/+3
| | | | | Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Move to a common linker scriptKumar Gala2009-08-28-0/+146
| | | | | | | | There are really no differences between all the 85xx linker scripts so we can just move to a single common one. Board code is still able to override the common one if need be. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added P1020 Processor Support.Poonam Aggrwal2009-08-28-1/+2
| | | | | | | | | | | | | | P1020 is another member of QorIQ series of processors which falls in ULE category. It is an e500 based dual core SOC. Being a scaled down version of P2020 it has following differences: - 533MHz - 800MHz core frequency. - 256Kbyte L2 cache - Ethernet controllers with classification capabilities. Also the SOC is pin compatible with P2020 Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Removed CONFIG_NUM_CPUS from 85xx/86xxPoonam Aggrwal2009-08-28-17/+39
| | | | | | | | | | | | | The number of CPUs are getting detected dynamically by checking the processor SVR value. Also removed CONFIG_NUM_CPUS references from all the platforms with 85xx/86xx processors. This can help to use the same u-boot image across the platforms. Also revamped and corrected few Freescale Copyright messages. Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Refactored common cpu specific code for 85xx/86xx into one file.Poonam Aggrwal2009-08-28-69/+1
| | | | | | | | Removed same code pieces from cpu/mpc85xx/cpu.c and cpu/mpc86xx/cpu.c and moved to cpu/mpc8xxx/cpu.c(new file) Signed-off-by: Poonam Aggrwal <poonam.aggrwal@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove redudant PLATFORM_CPPFLAGSKumar Gala2009-08-28-2/+1
| | | | | | | | | | | | | For historic reasons we had defined some additional PLATFORM_CPPFLAGS like: PLATFORM_CPPFLAGS += -DCONFIG_E500=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC85xx=1 PLATFORM_CPPFLAGS += -DCONFIG_MPC8548=1 However these are all captured in the config.h and thus redudant. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Prepare 2009.08-rc3v2009.08-rc3Wolfgang Denk2009-08-22-1/+1
| | | | | | Update CHANGELOG, minor Coding Style cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Fix addrmap to include memoryKumar Gala2009-08-14-6/+22
| | | | | | | | | | | | | | When we init the addrmap based on the TLB we will not end up getting the TLB that covers memory if we are using SPD. The reason is we haven't relocated at the point that we setup the memory TLB and thus it will not get setup in the addrmap. Instead we can just walk over the TLB array after we've relocated and see all the TLBs that have been set and use that information to populate the initial addrmap. By doing this we insure that we get the TLB entries that cover memory. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update Freescale copyrights to remove "All Rights Reserved"Kumar Gala2009-07-29-1/+1
| | | | | | "All Rights Reserved" conflicts with the GPL. Signed-off-by: Kumar Gala <kumar.gala@freescale.com>
* fsl_dma: Break out common memory initialization functionPeter Tyser2009-07-01-25/+1
| | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Move dma_init() call to common codePeter Tyser2009-07-01-3/+3
| | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl_dma: Move dma function prototypes to common header filePeter Tyser2009-07-01-4/+0
| | | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Rename dma_xfer() to dmacpy()Peter Tyser2009-07-01-15/+14
| | | | | | | | Also update dmacpy()'s argument order to match memcpy's and use phys_addr_t/phy_size_t for address/size arguments Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 8xxx: Break out DMA code to a common filePeter Tyser2009-07-01-47/+0
| | | | | | | | DMA support is now enabled via the CONFIG_FSL_DMA define instead of the previous CONFIG_DDR_ECC Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl/85xx, 86xx: Sync up DMA codePeter Tyser2009-06-12-4/+4
| | | | | | | | | | | | | | | | | | | | | The following changes were made to sync up the DMA code between the 85xx and 86xx architectures which will make it easier to break out common 8xxx DMA code: 85xx: - Don't set STRANSINT and SPCIORDER fields in SATR register. These bits only have an affect when the SBPATMU bit is set. - Write 0xffffffff instead of 0xfffffff to clear errors in the DMA status register. We may as well clear all 32 bits of the register... 86xx: - Add CONFIG_SYS_MPC86xx_DMA_ADDR define to address DMA registers - Add clearing of errors in the DMA status register when initializing the controller - Clear the channel start bit in the DMA mode register after a transfer Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl: Create common fsl_dma.h for 85xx and 86xx cpusPeter Tyser2009-06-12-14/+17
| | | | | | | | Break out DMA structures for the Freescale MPC85xx and MPC86xx cpus to reduce a large amount of code duplication Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* qe: Pass in uec_info struct through uec_initializeHaiying Wang2009-06-12-17/+4
| | | | | | | | | | | The uec driver contains code to hard code configuration information for the uec ethernet controllers. This patch creates an array of uec_info structures, which are then parsed by the corresponding driver instance to determine configuration. It also creates function uec_standard_init() to initialize all UEC interfaces for 83xx and 85xx. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add QE clk supportHaiying Wang2009-06-12-1/+18
| | | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Acked-by: Timur Tabi <Timur@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Added MPC8535/E identifiersKumar Gala2009-06-12-0/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Always attempt ethernet device tree fixupKumar Gala2009-06-12-3/+0
| | | | | | | | | | | Its reasonable that we may have ethernet devices but dont have drivers or support enabled for them in u-boot and want the device tree fixed up. Unconditionally calling the ethernet fixup is fine since if we dont have ethernet nodes that match (or aliases) we will not attempt to do anything. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Timur Tabi <timur@freescale.com>
* 85xx: Use print_size to report amount of memory not mapped by TLBsKumar Gala2009-06-12-1/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: bugfix for reading maximum TLB size on mpc85xxFredrik Arnerup2009-06-09-1/+1
| | | | | | | | | | | | | The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits. This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum (256 MB) which made u-boot hang in board_init_f() when trying to create a new stack in RAM. I have an mpc8540 with one 1GB dimm. Signed-off-by: Fredrik Arnerup <fredrik.arnerup@edgeware.tv> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Introduce determine_mp_bootpg() helper.Kumar Gala2009-04-01-23/+16
| | | | | | | | | | | | Match determine_mp_bootpg() that was added for 86xx. We need this to address a bug introduced in v2009.03 with 86xx MP booting. We have to make sure to reserve the region of memory used for the MP bootpg() so other u-boot code doesn't use it. Also added a comment about how cpu_reset() is dealing w/an errata on early 85xx MP HW. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC85xx: Add MPC8569 CPU supportHaiying Wang2009-03-30-0/+52
| | | | | | | | | There is a workaround for MPC8569 CPU Errata, which needs to set Bit 13 of LBCR in 4K bootpage. We setup a temp TLB for eLBC controller in bootpage, then invalidate it after LBCR bit 13 is set. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add support for additional e500mc featuresKumar Gala2009-03-30-1/+94
| | | | | | | * Enable backside L2 * e500mc no longer has timebase enable in HID (moved to CCSR register) Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-30-2/+4
| | | | | | | | | - support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
* Fix mpc85xx ddr-gen3 ddr_sdram_cfg.Ed Swarthout2009-03-09-2/+2
| | | | | | | Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* Coding style cleanup, update CHANGELOGWolfgang Denk2009-02-19-1/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Add eSDHC support for 8536 DSAndy Fleming2009-02-16-0/+15
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* 32bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b108122009-02-16-1/+8
| | | | | | | This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
* mpc85xx: Add support for the P2020Srikanth Srinivasan2009-02-16-0/+3
| | | | | | | | | | | Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-47/+27
| | | | | | | | | Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Format cpu freq printing to handle 8 coresKumar Gala2009-02-16-3/+5
| | | | | | | Only print 4 cpu freq per line. This way when we have 8 cores its a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add secondary CPUs processor frequency for e500 coreHaiying Wang2009-01-23-8/+24
| | | | | | | | | This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-4/+12
| | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-4/+12
| | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang2009-01-13-1/+5
| | | | | | | So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho2008-12-19-26/+32
| | | | | | | | | | | | | | | | | | | | | | | Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* mpc8568: Double local bus clock dividerTrent Piepho2008-12-19-2/+2
| | | | | | | | | | | | | The clock divider for the MPC8568 local bus should be doubled, like the other newer MPC85xx chips. Since there are now more chips with a 2x divider than a 1x, and any new 85xx chips will probably be 2x, invert the sense of the #if so that it lists the 1x chips instead of the 2x ones. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: Fix the boot window issueDave Liu2008-12-19-8/+8
| | | | | | | | | | | | | | | | | | | | | | If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: Dave Liu <daveliu@freescale.com>
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