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* fsl-ddr: add the DDR3 SPD infrastructureDave Liu2009-03-30-2/+4
| | | | | | | | | - support mirrored DIMMs, not support register DIMMs - test passed on P2020DS board with MT9JSF12872AY-1G1D1 - test passed on MPC8569MDS board with MT8JSF12864HY-1G1D1 Signed-off-by: Dave Liu <daveliu@freescale.com> Signed-off-by: Travis Wheatley <travis.wheatley@freescale.com>
* Fix mpc85xx ddr-gen3 ddr_sdram_cfg.Ed Swarthout2009-03-09-2/+2
| | | | | | | Commit e1be0d25, "32bit BUg fix for DDR2 on 8572" prevented other sdram_cfg bits (such as ecc and self_refresh_in_sleep) from being set. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* Coding style cleanup, update CHANGELOGWolfgang Denk2009-02-19-1/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Add eSDHC support for 8536 DSAndy Fleming2009-02-16-0/+15
| | | | Signed-off-by: Andy Fleming <afleming@freescale.com>
* 32bit BUg fix for DDR2 on 8572Poonam_Aggrwal-b108122009-02-16-1/+8
| | | | | | | This errata fix is required for 32 bit DDR2 controller on 8572. May also be required for P10XX20XX platforms Signed-off-by: Poonam_Agarwal-b10812 <b10812@lc1106.zin33.ap.freescale.net>
* mpc85xx: Add support for the P2020Srikanth Srinivasan2009-02-16-0/+3
| | | | | | | | | | | Added various p2020 processor specific details: * SVR for p2020, p2020E * immap updates for LAWs and DDR on p2020 * LAW defines related to p2020 Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Travis Wheatley <Travis.Wheatley@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-47/+27
| | | | | | | | | Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Format cpu freq printing to handle 8 coresKumar Gala2009-02-16-3/+5
| | | | | | | Only print 4 cpu freq per line. This way when we have 8 cores its a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add secondary CPUs processor frequency for e500 coreHaiying Wang2009-01-23-8/+24
| | | | | | | | | This patch updates e500 freqProcessor to array based on CONFIG_NUM_CPUS, and prints each CPU's frequency separately. It also fixes up each CPU's frequency in "clock-frequency" of fdt blob. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-4/+12
| | | | | | | Use CONFIG_SYS_PCI*_IO_BUS for the bus relative address instead of _IO_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-4/+12
| | | | | | | | Use CONFIG_SYS_{PCI,RIO}_MEM_BUS for the bus relative address instead of _MEM_BASE so we are more explicit. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang2009-01-13-1/+5
| | | | | | | So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho2008-12-19-26/+32
| | | | | | | | | | | | | | | | | | | | | | | Currently MPC85xx and MPC86xx boards just calculate the localbus frequency and print it out, but don't save it. This changes where its calculated and stored to be more consistent with the CPU, CCB, TB, and DDR frequencies and the MPC83xx localbus clock. The localbus frequency is added to sysinfo and calculated when sysinfo is set up, in cpu/mpc8[56]xx/speed.c, the same as the other frequencies are. get_clocks() copies the frequency into the global data, as the other frequencies are, into a new field that is only enabled for MPC85xx and MPC86xx. checkcpu() in cpu/mpc8[56]xx/cpu.c will print out the local bus frequency from sysinfo, like the other frequencies, instead of calculating it on the spot. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* mpc8568: Double local bus clock dividerTrent Piepho2008-12-19-2/+2
| | | | | | | | | | | | | The clock divider for the MPC8568 local bus should be doubled, like the other newer MPC85xx chips. Since there are now more chips with a 2x divider than a 1x, and any new 85xx chips will probably be 2x, invert the sense of the #if so that it lists the 1x chips instead of the 2x ones. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: Fix the boot window issueDave Liu2008-12-19-8/+8
| | | | | | | | | | | | | | | | | | | | | | If one custom board is using the 8MB flash, it is set as FLASH_BASE = 0xef000000, TEXT_BASE = 0xef780000. The current start.S code will be broken at switch_as. It is because the TLB1[15] is set as 16MB page size, EPN = TEXT_BASE & 0xff000000, RPN = 0xff000000. For the 8MB flash case, the EPN = 0xefxxxxxx, RPN = 0xffxxxxxx. Assume the virt address of switch_as is 0xef7ff18c, the real address of the instruction at switch_as should be 0xff7ff18c. the 0xff7ff18c is out of the range of the default 8MB boot LAW window 0xff800000 - 0xffffffff. So when we switch to AS1 address space at switch_as, the core can't fetch the instruction at switch_as any more. It will cause broken issue. Signed-off-by: Dave Liu <daveliu@freescale.com>
* Set IVPR to kenrel entry point in second core boot pageHaiying Wang2008-12-19-0/+1
| | | | | | | | | | | Assuming the OSes exception vectors start from the base of kernel address, and the kernel physical starting address can be relocated to an non-zero address. This patch enables the second core to have a valid IVPR for debugger before kernel setting IVPR in CAMP mode. Otherwise, IVPR is 0x0 and it is not a valid value for second core which runs kernel at different physical address other than 0x0. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-1/+1
| | | | | | | | | | | | | | On newer CPUs, 8536, 8572, and 8610, the CLKDIV field of LCRR is five bits instead of four. In order to avoid an ifdef, LCRR_CLKDIV is set to 0x1f on all systems. It should be safe as the fifth bit was defined as reserved and set to 0. Code that was using a hard coded 0x0f is changed to use LCRR_CLKDIV. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* mpc8[56]xx: Put localbus clock in device treeTrent Piepho2008-12-19-1/+7
| | | | | | | | | | | | | | | | | | | | | | | | | | | | Export the localbus frequency in the device tree, the same way the CPU, TB, CCB, and various other frequencies are exported in their respective device tree nodes. Some localbus devices need this information to be programed correctly, so it makes sense to export it along with the other frequencies. Unfortunately, when someone wrote the localbus dts bindings, they didn't bother to define what the "compatible" property should be. So it seems no one was quite sure what to put in their dts files. Based on current existing dts files in the kernel source, I've used "fsl,pq3-localbus" and "fsl,elbc" for MPC85xx, which are used by almost all of the 85xx devices, and are looked for by the Linux code. The eLBC is apparently not entirely backward compatible with the pq3 LBC and so eLBC equipped platforms like 8572 won't use pq3-localbus. For MPC86xx, I've used "fsl,elbc" which is used by some of the 86xx systems and is also looked for by the Linux code. On MPC8641, I've also used "fsl,mpc8641-localbus" as it is also commonly used in dts files, some of which don't use "fsl,elbc" or any other acceptable name to match on. Signed-off-by: Trent Piepho <tpiepho@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* 85xx: Add support to populate addr map based on TLB settingsKumar Gala2008-12-19-0/+34
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-1/+2
| | | | | | | Use the GNU 'date' command to auto-generate a new U-Boot timestamp on every compile. Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* 85xx: init gd as early as possibleKumar Gala2008-12-04-6/+6
| | | | | | | | Moved up the initialization of GD so C code like set_tlb() can use gd->flags to determine if we've relocated or not in the future. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Fix relocation of CCSRBARKumar Gala2008-12-04-4/+5
| | | | | | | | | | If the virtual address for CCSRBAR is the same after relocation but the physical address is changing we'd end up having two TLB entries with the same VA. Instead we new us the new CCSRBAR virt address + 4k as a temp virt address to access the old CCSRBAR to relocate it. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add PORDEVSR_PCI1 definePeter Tyser2008-12-04-1/+1
| | | | | | | | | Add define used to determine if PCI1 interface is in PCI or PCIX mode. Convert users of the old PORDEVSR_PCI constant to use MPC85xx_PORDEVSR_PCI1 Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Add CPU 2 errata workaround to all 8548 boardsPeter Tyser2008-12-03-0/+13
| | | | | | | | | | | All mpc8548-based boards should implement the suggested workaround to CPU 2 errata. Without the workaround, its possible for the 8548's core to hang while executing a msync or mbar 0 instruction and a snoopable transaction from an I/O master tagged to make quick forward progress is present. Signed-off-by: Peter Tyser <ptyser@xes-inc.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Moved initialization of QE Ethernet controller to cpu_eth_init()Ben Warren2008-11-09-0/+18
| | | | | | Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Moved initialization of FCC Ethernet controller to cpu_eth_initBen Warren2008-11-09-1/+4
| | | | | | | | | | | Affected boards: Several MPC8xx boards Several MPC8260/MPC8272 boards Several MPC85xx boards Removed initialization of the driver from net/eth.c Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* Fix typo in cpu/mpc85xx/cpu.cBen Warren2008-11-09-1/+1
| | | | | | CONFIG_MPC85xx_FEC -> CONFIG_MPC85XX_FEC Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* 85xx: Fix the incorrect register used for DDR erratum1Dave Liu2008-10-24-3/+6
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The 8572 DDR erratum1: DDR controller may enter an illegal state when operating in 32-bit bus mode with 4-beat bursts. Description: When operating with a 32-bit bus, it is recommended that DDR_SDRAM_CFG[8_BE] is cleared when DDR2 memories are used. This forces the DDR controller to use 4-beat bursts when communicating to the DRAMs. However, an issue exists that could lead to data corruption when the DDR controller is in 32-bit bus mode while using 4-beat bursts. Projected Impact: If the DDR controller is operating in 32-bit bus mode with 4-beat bursts, then the controller may enter into a bad state. All subsequent reads from memory is corrupted. Four-beat bursts with a 32-bit bus only is used with DDR2 memories. Therefore, this erratum does not affect DDR3 mode. Work Arounds: To work around this issue, software must set DEBUG_1[31] in DDR memory mapped space (CCSRBAR offset + 0x2f00 for DDR_1 and CCSRBAR offset + 0x6f00 for DDR_2). Currenlty, the code is using incorrect register DDR_SDRAM_CFG_2 as condition, but it should be DDR_SDRAM_CFG register. Signed-off-by: Dave Liu <daveliu@freescale.com>
* 85xx: Add basic e500mc core supportKumar Gala2008-10-24-0/+14
| | | | | | | | | | | Introduce CONFIG_E500MC to deal with the minor differences between e500v2 and e500mc. * Certain fields of HID0/1 don't exist anymore on e500mc * Cache line size is 64-bytes on e500mc * reset value of PIR is different Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic numberKumar Gala2008-10-24-2/+2
| | | | | | | Using CONFIG_SYS_CACHELINE_SIZE instead of 31 means we can handle e500mc's 64-byte cacheline properly when it gets added. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Use strmhz() to format clock frequenciesWolfgang Denk2008-10-21-11/+15
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Merge 'next' branchWolfgang Denk2008-10-18-156/+221
|\ | | | | | | | | | | | | | | | | Conflicts: board/freescale/mpc8536ds/mpc8536ds.c include/configs/mgcoge.h Signed-off-by: Wolfgang Denk <wd@denx.de>
| * 85xx if NUM_CPUS>1, print cpu numberEd Swarthout2008-10-18-0/+5
| | | | | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
| * Have u-boot pass stashing parameters into device treeAndy Fleming2008-10-18-0/+11
| | | | | | | | | | | | | | | | | | Some cores don't support ethernet stashing at all, and some instances have errata. Adds 3 properties to gianfar nodes which support stashing. For now, just add this support to 85xx SoCs. Signed-off-by: Andy Fleming <afleming@freescale.com>
| * 85xx: Export invalidate_{i,d}cache and add flush_dcacheKumar Gala2008-10-18-0/+49
| | | | | | | | | | | | | | | | Added the ability for C code to invalidate the i/d-cache's and to flush the d-cache. This allows us to more efficient change mappings from cache-able to cache-inhibited. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-156/+156
| | | | | | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* | Revert "85xx: Using proper I2C source clock divider for MPC8544"Kumar Gala2008-10-17-2/+2
|/ | | | | | | | | | This reverts commit dffd2446fb041f38ef034b0fcf41e51e5e489159. The fix introduced by this patch is not correct. The problem is that the documentation is not correct for the MPC8544 with regards to which bit in PORDEVSR2 is for the SEC_CFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Using proper I2C source clock divider for MPC8544Wolfgang Grandegger2008-10-08-2/+2
| | | | | | | | | Measurements with our MPC8544 board showed that the I2C bus frequency is wrong by a factor of 1.5. Obviously, the interpretation of the MPC85xx_PORDEVSR2_SEC_CFG bit of the cfg_sec_freq register is not correct. There seems to be an error in the 8544 RM. Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* Fix the incorrect DDR clk freq reporting on 8536DSJason Jin2008-10-07-2/+4
| | | | | | | | | On 8536DS board, When the DDR clk is set async mode(SW3[6:8] != 111), The display is still sync mode DDR freq. This patch try to fix this. The display DDR freq is now the actual freq in both sync and async mode. Signed-off-by: Jason Jin <Jason.jin@freescale.com>
* 85xx: Remove setting of *cache-line-size in device treesKumar Gala2008-10-07-3/+0
| | | | | | | ePAPR says if the *cache-block-size is the same as *cache-line-size than we don't need the *cache-line-size property. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix printf errors under -DDEBUGAndrew Klossner2008-09-09-7/+7
| | | | | | | | | | | | Fix printf format-string/arg mismatches under -DDEBUG. These warnings occur with DEBUG defined for a platform using cpu/mpc85xx. Users of other architectures can unearth similar problems by adding the line "CFLAGS += -DDEBUG=1" in config.mk right after "CFLAGS += $(call cc-option,-fno-stack-protector)". Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Ensure timebase is zero on secondary coresKumar Gala2008-09-09-0/+5
| | | | | | | The e500um says the timebase is volatile out of reset. To ensure TB sync works we need to make sure its zero. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.Sergei Poselenov2008-09-08-8/+7
| | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* Pass in tsec_info struct through tsec_initializeAndy Fleming2008-09-02-23/+10
| | | | | | | | | | | | | The tsec driver contains a hard-coded array of configuration information for the tsec ethernet controllers. We create a default function that works for most tsecs, and allow that to be overridden by board code. It creates an array of tsec_info structures, which are then parsed by the corresponding driver instance to determine configuration. Also, add regs, miiregs, and devname fields to the tsec_info structure, so that we don't need the kludgy "index" parameter. Signed-off-by: Andy Fleming <afleming@freescale.com> Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* mpc85xx: remove redudant code with lib_ppc/interrupts.cKumar Gala2008-08-27-97/+12
| | | | | | | | | | For some reason we duplicated the majority of code in lib_ppc/interrupts.c not show how that happened, but there is no good reason for it. Use the interrupt_init_cpu() and timer_interrupt_cpu() since its why they exist. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* mpc85xx: Add support for the MPC8536Kumar Gala2008-08-27-1/+199
| | | | | | | | | | | The MPC8536 Adds SDHC and SATA controllers to the PQ3 family. We also have SERDES init code for the 8536. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Jason Jin <Jason.jin@freescale.com> Signed-off-by: Dave Liu <daveliu@freescale.com>
* mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-2/+2
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Remove old SPD support from cpu/mpc85xxKumar Gala2008-08-27-1166/+0
| | | | | | | All 85xx boards have been converted to the new code so we can remove the old SPD DDR setup code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add 85xx specific register settingKumar Gala2008-08-27-0/+318
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* FSL DDR: Add e500 TLB helper for DDR codeKumar Gala2008-08-27-0/+64
| | | | | | | Provide a helper function that board code can call to map TLBs when setting up DDR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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