summaryrefslogtreecommitdiff
path: root/cpu/mpc85xx
Commit message (Collapse)AuthorAgeLines
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-1/+10
| | | | | | | | | | | | | | | | | | | | | | | | | | | | The main purpose of this rewrite it to be able to share the same initialization code on all FSL PowerPC products that have DDR controllers. (83xx, 85xx, 86xx). The code is broken up into the following steps: GET_SPD COMPUTE_DIMM_PARMS COMPUTE_COMMON_PARMS GATHER_OPTS ASSIGN_ADDRESSES COMPUTE_REGS PROGRAM_REGS This allows us to share more code an easily allow for board specific code overrides. Additionally this code base adds support for >4G of DDR and provides a foundation for supporting interleaving on processors with more than one controller. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Signed-off-by: Becky Bruce <becky.bruce@freescale.com> Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* fdt: rework fdt_fixup_ethernet() to use env instead of bd_tKumar Gala2008-08-21-1/+1
| | | | | | | | | | Move to using the environment variables 'ethaddr', 'eth1addr', etc.. instead of bd->bi_enetaddr, bi_enet1addr, etc. This makes the code a bit more flexible to the number of ethernet interfaces. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Rename CONFIG_NR_CPUS to CONFIG_NUM_CPUSKumar Gala2008-08-12-3/+3
| | | | | | | Use CONFIG_NUM_CPUS to match existing define used by 86xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Jon Loeliger <jdl@freescale.com>
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-07-15-23/+42
|\
| * 85xx: Cleanup L2 cache size detectionKumar Gala2008-07-14-17/+30
| | | | | | | | | | | | | | | | | | | | The L2 size detection code was a bit confusing and we kept having to add code to it to handle new processors. Change the sense of detection so we look for the older processors that aren't changing. Also added support for 1M cache size on 8572. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
| * 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreqPaul Gortmaker2008-07-14-1/+1
| | | | | | | | | | | | | | | | | | | | Some boards that have external 16550 UARTs don't have a direct tie between bi_busfreq and the clock used for the UARTs. Boards that do have such a tie should set CFG_NS16550_CLK to be get_bus_freq(0) -- which most of them do already. Signed-off-by: Paul Gortmaker <paul.gortmaker@windriver.com> Acked-by: Kim Phillips <kim.phillips@freescale.com>
| * Change the temp map to ROM to align addresses to page size.Andrew Klossner2008-07-14-4/+5
| | | | | | | | | | | | | | | | | | | | With a page size of BOOKE_PAGESZ_16M, both the real and effective addresses must be multiples of 16MB. The hardware silently truncates them so the code happens to work. This patch clarifies the situation by establishing addresses that the hardware doesn't need to truncate. Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
| * mpc85xx: use IS_E_PROCESSOR macroKim Phillips2008-07-14-1/+1
| | | | | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
| * fdt: add crypto node handling for MPC8{3, 5}xxE processorsKim Phillips2008-07-14-0/+5
| | | | | | | | | | | | | | | | Delete the crypto node if not on an E-processor. If on 8360 or 834x family, check rev and up-rev crypto node (to SEC rev. 2.4 property values) if on an 'EA' processor, e.g. MPC8349EA. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | Fix some more printf() format problems.Kumar Gala2008-07-14-2/+2
|/ | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix printf errors.Andrew Klossner2008-07-09-4/+4
| | | | | | | | | | | | The compiler will help find mismatches between printf formats and arguments if you let it. This patch adds the necessary attributes to declarations in include/common.h, then begins to correct the resulting compiler warnings. Some of these were bugs, e.g., "$d" instead of "%d" and incorrect arguments. Others were just annoying, like int-long mismatches on a system where both are 32 bits. It's worth fixing the annoying errors to catch the real ones. Signed-off-by: Andrew Klossner <andrew@cesa.opbu.xerox.com>
* Merge branch 'master' of git://www.denx.de/git/u-boot-netWolfgang Denk2008-07-09-0/+30
|\
| * Add mechanisms for CPU and board-specific Ethernet initializationBen Warren2008-07-06-0/+30
| | | | | | | | | | | | | | | | This patch is the first step in cleaning up net/eth.c, by moving Ethernet initialization to CPU or board-specific code. Initial implementation is only on the Freescale TSEC controller, but others will be added soon. Signed-off-by: Ben Warren <biggerbadderben@gmail.com>
* | Coding Style CleanupWolfgang Denk2008-06-28-1/+1
|/ | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Fix 4xx build issueAnatolij Gustschin2008-06-19-1/+1
| | | | | | | | | | | | | | Building for 4xx doesn't work since commit 4dbdb768: In file included from 4xx_pcie.c:28: include/asm/processor.h:971: error: expected ')' before 'ver' make[1]: *** [4xx_pcie.o] Error 1 This patch fixes the problem. Signed-off-by: Anatolij Gustschin <agust@denx.de> Acked-by: Stefan Roese <sr@denx.de> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/86xx: Move to dynamic mgmt of LAWsKumar Gala2008-06-11-1/+1
| | | | | | | | | | | With the new LAW interface (set_next_law) we can move to letting the system allocate which LAWs are used for what purpose. This makes life a bit easier going forward with the new DDR code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Jon Loeliger <jdl@freescale.com> Acked-by: Becky Bruce <becky.bruce@freescale.com>
* FSL LAW: Keep track of LAW allocationsKumar Gala2008-06-11-17/+6
| | | | | | | | | | | | | | | Make it so we keep track of which LAWs have allocated and provide a function (set_next_law) which can allocate a LAW for us if one is free. In the future we will move to doing more "dynamic" LAW allocation since the majority of users dont really care about what LAW number they are at. Also, add CONFIG_MPC8540 or CONFIG_MPC8560 to those boards which needed them Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Added the upmconfig() function for 85xx.Sergei Poselenov2008-06-11-0/+66
| | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* MPC85xx: Beautify boot output of L2 cache configurationWolfgang Grandegger2008-06-10-9/+11
| | | | | | | | | | The boot output is now aligned poperly with other boot output lines, e.g.: FLASH: 128 MB L2: 512 KB enabled Signed-off-by: Wolfgang Grandegger <wg@grandegger.com>
* 85xx: Add setting of cache props in the device tree.Kumar Gala2008-06-10-0/+128
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: expose cpu identificationKumar Gala2008-06-10-36/+40
| | | | | | | | | | | | | The current cpu identification code is used just to return the name of the processor at boot. There are some other locations that the name is useful (device tree setup). Expose the functionality to other bits of code. Also, drop the 'E' suffix and add it on by looking at the SVR version when we print this out. This is mainly to allow the most flexible use of the name. The device tree code tends to not care about the 'E' suffix. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Only use PORPLLSR[DDR_Ratio] on platforms that define itKumar Gala2008-06-09-2/+6
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC85xx: Change traps.c to not reference non-addressable memoryBecky Bruce2008-06-09-3/+5
| | | | | | | | | | | Currently, END_OF_RAM is used by the trap code to determine if we should attempt to access the stack pointer or not. However, on systems with a lot of RAM, only a subset of the RAM is guaranteed to be mapped in and accessible. Change END_OF_RAM to use get_effective_memsize() instead of using the raw ram size out of the bd. Signed-off-by: Becky Bruce <becky.bruce@freescale.com>
* Merge branch 'socrates' of /home/wd/git/u-boot/projectsWolfgang Denk2008-05-21-9/+14
|\
| * Fixed reset for socratesSergei Poselenov2008-05-20-9/+14
| | | | | | | | Signed-off-by: Sergei Poselenov <sposelenov@emcraft.com>
* | Big white-space cleanup.Wolfgang Denk2008-05-21-2/+2
|/ | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Add -mno-spe to e500/85xx buildsKumar Gala2008-04-29-0/+1
| | | | | | | | | | | Newer gcc's might be configured to enable autovectorization by default. If we happen to build with one of those compilers we will get SPE instructions in random code. -mno-spe disables the compiler for automatically generating SPE instructions without our knowledge. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docsKumar Gala2008-04-29-2/+2
| | | | | | | All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Additional fixes and cleanup of MP codeKumar Gala2008-04-29-2/+7
| | | | | | | | | | | | | | | | | * adjust __spin_table alignment to match ePAPR v0.94 spec * loop over all cpus when determing who is up. This fixes an issue if the "boot cpu" isn't core0. The "boot cpu" will already be in the cpu_up_mask so there is no harm * Added some protection in the code to ensure proper behavior. These changes are explicitly needed but don't hurt: - Added eieio to ensure the "hot word" of the table is written after all other table updates have occurred. - Added isync to ensure we don't prefetch loading of table entries until we a released These issues we raised by Dave Liu. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Round up frequency calculations to get reasonable outputKumar Gala2008-04-24-7/+6
| | | | | | | | | | | eg. because of rounding error we can get 799Mhz instead of 800Mhz. Introduced DIV_ROUND_UP and roundup taken from linux kernel. Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Fix size of cpu-release-addr propertyKumar Gala2008-04-18-1/+1
| | | | | The cpu-release-addr is defined as always being a 64-bit quanity regardless if we are running on a 32-bit or 64-bit machine.
* Fix calculation of I2C clock for some 85xx chipsTimur Tabi2008-04-18-1/+30
| | | | | | | | | | | Some 85xx chips use CCB as the base clock for the I2C. Some use CCB/2, and some use CCB/3. There is no pattern that can be used to determine which chips use which frequency, so the only way to determine is to look up the actual SOC designation and use the right value for that SOC. Update immap_85xx.h to include the GUTS PORDEVSR2 register. Signed-off-by: Timur Tabi <timur@freescale.com>
* 85xx: Fix detection of MP cpu spin upKumar Gala2008-04-11-1/+5
| | | | | | | | We were looking at the wrong memory offset to determine of a secondary cpu had been spun up or not. Also added a warning message if the all the secondary cpus we expect don't spin up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use SVR_SOC_VER instead of SVR_VERKumar Gala2008-04-11-2/+2
| | | | | | | | The recent change introduced by 'Update SVR numbers to expand support' now requires that we use SVR_SOC_VER instead of SVR_VER if we want to compare against a particular processor id. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add cpu_mp_lmb_reserve helper to reserve boot pageKumar Gala2008-03-26-0/+15
| | | | | | | Provide a board_lmb_reserve helper function to ensure we reserve the page of memory we are using for the boot page translation code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Update multicore boot mechanism to ePAPR v0.81 specKumar Gala2008-03-26-64/+115
| | | | | | | | | | | | The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix merge duplicationKumar Gala2008-03-26-49/+0
| | | | | | ft_fixup_cpu() got duplicated in some merge snafu. Remove the duplicate. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Speed up get_ddr_freq() and get_bus_freq()James Yang2008-03-26-16/+5
| | | | | | | | | | get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were called. However, get_sys_info() recalculates extraneous information when called each time. Have get_ddr_freq() and get_bus_freq() return memoized values from global_data instead. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Show DDR memory data rate in addition to the memory clock frequency.James Yang2008-03-26-3/+6
| | | | | | | | | Show the DDR memory data rate in addition to the memory clock frequency. For DDR/DDR2 memories the memory data rate is 2x the memory clock. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: get_tbclk() speed up and rounding fixJames Yang2008-03-26-5/+3
| | | | | | | | | | Speed up get_tbclk() by referencing pre-computed bus clock frequency value from global data instead of sys_info_t. Fix rounding of result to nearest; previously it was rounding upwards. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update SVR numbers to expand supportAndy Fleming2008-03-26-37/+48
| | | | | | | | | | | | | FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+49
| | | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+405
| | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-26-3/+3
| | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Don't icbi when unlocking the cacheKumar Gala2008-02-27-5/+2
| | | | | | | | | There is no reason to icbi when invalidating the temporary stack in the d-cache. Its impossible on e500 to have the i-cache contain any addresses in the temp stack and it can be problematic in generating transactions on the bus to non-valid addresses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix source for ECM error IVPRAndy Fleming2008-02-27-1/+1
| | | | | | | | The source vector for the ECM was being set to 2, but that's what the source vector for DDR was being set to. Change it to 1. Signed-off-by: Andy Fleming <afleming@freescale.com>
* Invalidate INIT_RAM TLB mappingsAndy Fleming2008-02-27-0/+11
| | | | | | | | | | | | | | | Commit 0db37dc... (and some others) changed the INIT_RAM TLB mappings to be unguarded. This collided with an existing "bug" where the mappings for the INIT_RAM were being kept around. This meant that speculative loads to those addresses were succeeding in the TLB, and going out to the bus, where they were causing an exception (there's nothing at that address). The Flash code was coincidentally causing such a speculative load. Rather than go back to mapping the INIT RAM as guarded, we fix it so that the entries for the INIT_RAM are invalidated. Thus the speculative loads will fail in the TLB, and have no effect. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx, 86xx: Determine I2C clock frequencies and store in global_dataTimur Tabi2008-02-14-0/+3
| | | | | | | | | Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx. Update the get_clocks() function in 85xx and 86xx to determine the I2C clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk. Signed-off-by: Timur Tabi <timur@freescale.com>
* PPC: Use r2 instead of r29 as global data pointerWolfgang Denk2008-02-14-1/+2
| | | | | | | | | | | | R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc will refuse to use load/store multiple insns; instead, it issues a list of simple load/store instructions upon function entry and exit, resulting in bigger code size, which in turn makes the build for a few boards fail. Use r2 instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-45/+0
| | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
generated by cgit v1.1 at 2024-12-23 22:22:40 +0000