summaryrefslogtreecommitdiff
path: root/cpu/mpc85xx
Commit message (Collapse)AuthorAgeLines
* Enable L2 cache for MPC8568MDS boardHaiying Wang2007-08-29-1/+1
| | | | | | The L2 cache size is 512KB for 8568, print out the correct informaiton. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xxCDS: Add make targets for legacy systems.Randy Vinson2007-08-14-1/+1
| | | | | | | | The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson <rvinson@mvista.com>
* Add support for UEC to 8568Andy Fleming2007-08-14-2/+142
| | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Empirically set cpo and clk_adjust for mpc85xx DDR2 supportHaiying Wang2007-08-14-5/+7
| | | | | | | | | | | | | | This patch is against u-boot-mpc85xx.git of www.denx.com Setting cpo to 0x9 for frequencies higher than 333MHz is verified on both MPC8548CDS board and MPC8568MDS board, especially for supporting 533MHz DDR2. Setting clk_adjust to 0x6(3/4 late cycle) for MPC8568MDS board is for DDR2 on all current board versions especially ver 1.92 or later to bring up. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* Use an absolute address when jumping out of 4k boot pageKumar Gala2007-08-14-29/+24
| | | | | | | On e500 when we leave the 4k boot page we should use an absolute address since we don't know where the board code may want us to be really running at. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* MPC85xx BA bits not set for 3-bit bank address DIMMAndy Fleming2007-08-14-1/+6
| | | | | | | | | | The current implementation does not set the number of bank address bits (BA) in the processor. The default assumes 2 logical bank bits. This works fine for a DIMM that uses devices with 4 internal banks (SPD byte17 = 0x4) but needs to be set appropriately for a DIMM that uses devices with 8 internal banks (SPD byte17 = 0x8). Signed-off-by: Greg Davis <DavisG@embeddedplanet.com>
* Fix minor 85xx warningsAndy Fleming2007-08-14-1/+3
| | | | | | | | | | | Some patches had inserted warnings into the build: * mpc8560ads declared data without using it * cpu_init declared ecm and immap without using it in all CONFIGs * MPC8548CDS.h had its default filenames changed so that they contained "\m" in the paths. Made the defaults not Windows-specific (or anything-specific) Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx start.S cleanup and exception supportAndy Fleming2007-08-14-298/+319
| | | | | | | | | | | | | | | | | | | | | | | | | | From: Ed Swarthout <Ed.Swarthout@freescale.com> Support external interrupts from platform to eliminate system hangs. Define CONFIG_INTERRUPTS board configure option to enable. Enable ecm, ddr, lbc, and pci/pcie error interrupts in PIC. Remove extra cpu initialization redundant with hardware initialization. Whitespace cleanup. Define and use _START_OFFSET consistent with other processors using ppc_asm.tmpl Move additional code from .text to boot page to make room for exception vectors at start of image. Handle Machine Check, External and Critical exceptions. Fix e500 machine check error determination in traps.c TEXT_BASE can now be 0xfffc_0000 - which cuts binary image in half. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx allow debugger to configure ddr.Ed Swarthout2007-08-14-3/+45
| | | | | | | Only check for mpc8548 rev 1 when compiled for 8548. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* mpc85xx L2 cache reporting and SRAM relocation option.Ed Swarthout2007-08-14-18/+47
| | | | | | | | Allow debugger to override flash cs0/cs1 settings to enable alternate boot regions Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* cpu/ rtc/ include/: Remove lingering references to CFG_CMD_* symbols.Jon Loeliger2007-07-10-1/+1
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* cpu/m*: Remove obsolete references to CONFIG_COMMANDSJon Loeliger2007-07-09-12/+12
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Fix #if typo in CONFIG_CMD_* changes.Jon Loeliger2007-07-05-1/+1
| | | | Signed-off-by: Jon Loeliger <jdl@freescale.com>
* cpu/mpc*/ : Augment CONFIG_COMMANDS tests with defined(CONFIG_CMD_*).Jon Loeliger2007-07-04-11/+11
| | | | | | | | | | | | | | This is a compatibility step that allows both the older form and the new form to co-exist for a while until the older can be removed entirely. All transformations are of the form: Before: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) After: #if (CONFIG_COMMANDS & CFG_CMD_AUTOSCRIPT) || defined(CONFIG_CMD_AUTOSCRIPT) Signed-off-by: Jon Loeliger <jdl@freescale.com>
* Merge with /home/wd/git/u-boot/custodian/u-boot-testingWolfgang Denk2007-07-03-1/+1
|\
| * Reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECxKim Phillips2007-05-17-1/+1
| | | | | | | | | | | | | | For all practical u-boot purposes, TSECs don't differ throughout the mpc8[356]xx families; reduce CONFIG_MPC8YXX_TSECx to CONFIG_TSECx. Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
* | [ppc] Fix build breakage for all non-4xx PowerPC variants.Rafal Jaworowski2007-06-22-2/+2
|/ | | | | - adapt to the more generic EXCEPTION_PROLOG and CRIT_EXCEPTION macros - minor 4xx cleanup
* Coding stylke cleanup; update CHANGELOG.Wolfgang Denk2007-05-05-9/+9
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Cleaned up some 85xx PCI bugsAndy Fleming2007-05-02-4/+4
| | | | | | | | | | | * Cleaned up the CDS PCI Config Tables and added NULL entries to the end * Fixed PCIe LAWBAR assignemt to use the cpu-relative address * Fixed 85xx PCI code to assign powar region sizes based on the config values (rather than hard-coding them) * Fixed the 8548 CDS PCI2 IO to once again have 0 as the base address Signed-off-by: Andy Fleming <afleming@freescale.com>
* Add support for the 8568 MDS boardAndy Fleming2007-05-02-2/+7
| | | | | | | | | This included some changes to common files: * Add 8568 processor SVR to various places * Add support for setting the qe bus-frequency value in the dts * Add the 8568MDS target to the Makefile Signed-off-by: Andy Fleming <afleming@freescale.com>
* Reworked 85xx speed detection codeAndy Fleming2007-04-23-36/+8
| | | | | | | | | Changed the code to read the registers and calculate the clock rates, rather than using a "switch" statement. Idea from Andrew Klossner <andrew@cesa.opbu.xerox.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Support 1G size on 8548Andy Fleming2007-04-23-2/+9
| | | | | | | e500v2 and newer cores support 1G page sizes. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Only set ddrioovcr for 8548 rev1.Andy Fleming2007-04-23-6/+7
| | | | | Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* Tweak DDR ECC error counterAndy Fleming2007-04-23-2/+5
| | | | | | | Enable single-bit error counter when memory was cleared by ddr controller. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: write MAC address to mac-address and local-mac-addressTimur Tabi2007-04-23-0/+20
| | | | | | | | | Some device trees have a mac-address property, some have local-mac-address, and some have both. To support all of these device trees, ftp_cpu_setup() should write the MAC address to mac-address and local-mac-address, if they exist. Signed-off-by: Timur Tabi <timur@freescale.com>
* Some 85xx cpu cleanupsAndy Fleming2007-04-23-3/+8
| | | | | | | | | * Cleaned up the TSR[WIS] clearing * Cleaned up DMA initialization Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* Add cpu support for the 8544Andy Fleming2007-04-23-2/+8
| | | | | | | | Recognize new SVR values, and add a few register definitions Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com> Signed-off-by: Jon Loeliger <jdl@freescale.com> Acked-by: Andy Fleming <afleming@freescale.com>
* u-boot: Fix e500 v2 core reset bugZang Roy-r619112007-04-23-6/+15
| | | | | | | | The following patch fixes the e500 v2 core reset bug. For e500 v2 core, a new reset control register is added to reset the processor. Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* u-boot: v2: Remove the fixed TLB and LAW entrynubmerZang Roy-r619112007-04-23-12/+4
| | | | | | | | | Remove the fixed TLB and LAW entry nubmer. Use actually TLB and LAW entry number to control the loop. This can reduce the potential risk for the 85xx processor increasing its TLB adn LAW entry number. Signed-off-by: Swarthout Edward <swarthout@freescale.com> Signed-off-by: Roy Zang <tie-fei.zang@freescale.com>
* Code cleanupWolfgang Denk2006-10-24-1/+1
|
* Converted all 85xx boards to use a common FSL I2C driver.Jon Loeliger2006-10-20-266/+1
| | | | | | | | Introduced COFIG_FSL_I2C to select the common FSL I2C driver. And removed hard i2c path from a few u-boot.lds scipts too. Minor whitespace cleanups along the way. Signed-off-by: Jon Loeliger <jdl@freescale.com>
* * Fix a bunch of compiler warnings for gcc 4.0Jon Loeliger2006-10-19-0/+5
| | | | Signed-off-by: Matthew McClintock <msm@freescale.com>
* Merge branch 'master' of http://www.denx.de/git/u-bootJon Loeliger2006-10-10-1/+1
|\
| * Move "ar" flags to config.mk to allow for silent "make -s"Wolfgang Denk2006-10-09-1/+1
| | | | | | | | Based on patch by Mike Frysinger, 20 Jun 2006
* | Coding style changes to remove local varible blocksJon Loeliger2006-10-10-70/+64
| | | | | | | | and reformat a bit nicer.
* | Merge branch 'master' of http://www.denx.de/git/u-bootJon Loeliger2006-09-19-6/+12
|\ \ | |/ | | | | | | | | Conflicts: board/stxxtc/Makefile
| * Add support for a saving build objects in a separate directory.Marian Balakowicz2006-09-01-6/+12
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | Modifications are based on the linux kernel approach and support two use cases: 1) Add O= to the make command line 'make O=/tmp/build all' 2) Set environement variable BUILD_DIR to point to the desired location 'export BUILD_DIR=/tmp/build' 'make' The second approach can also be used with a MAKEALL script 'export BUILD_DIR=/tmp/build' './MAKEALL' Command line 'O=' setting overrides BUILD_DIR environent variable. When none of the above methods is used the local build is performed and the object files are placed in the source directory.
* | * Switched default PCI speed for 8540 ADS back to 33MHzMatthew McClintock2006-08-09-0/+3
| | | | | | | | | | | | | | | | * Added comments and a printf to warn that PCI-X won't work at 33MHz Patch by Andy Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* | * Added support for initializing second PCI bus on 85xx Patch by Andy ↵Matthew McClintock2006-08-09-35/+147
| | | | | | | | | | | | Fleming 17-Mar-2006 Signed-off-by: Andy Fleming <afleming@freescale.com>
* | * Add Flat Dev Tree construction for MPC85xx ADS and CDS boards Patch by Jon ↵Matthew McClintock2006-08-09-1/+50
|/ | | | | | Loeliger 17-Jan-2006 Signed-off-by: Jon Loeliger <jdl@freescale.com>
* GCC-4.x fixes: clean up global data pointer initialization for all boards.Wolfgang Denk2006-03-31-13/+10
|
* Fix bug in [id]cache_status commands for MPC85xx processors;Wolfgang Denk2006-03-13-2/+2
| | | | | | should look at LSB of L1CSRn registers to determine if L1 cache is enabled, not the MSB. Patch by Murray Jensen, 19 Jul 2005
* Fix DPRAM offset/size for MPC8541/8555.Wolfgang Denk2005-12-06-1/+3
| | | | Simplify TQM85xx Makefile handling.
* Fix MPC85xx PCI support (pci_register_hose() before pci config access)Stefan Roese2005-11-07-10/+10
| | | | Patch by Stefan Roese, 07 Nov 2005
* Add support for multiple PHYs.Marian Balakowicz2005-10-28-0/+10
|
* Cleanup for GCC-4.xWolfgang Denk2005-10-13-2/+2
|
* Added support for KwikByte KB920x boards (based on AT91RM9200)Wolfgang Denk2005-10-05-1/+1
| | | | Patch by Matt ?? <kb9200_dev@kwikbyte.com>, 27 Apr 2005
* E500 update: repoint IVPR to RAM when code is relocatedWolfgang Denk2005-10-05-0/+5
| | | | Patch by Kylo Ginsberg, 13 Apr 2005
* Merge with /home/wd/git/u-boot/masterWolfgang Denk2005-08-05-2/+2
|\
| * Fix typos in cpu/85xx/start.S which caused DataTLB exception to beWolfgang Denk2005-08-04-2/+2
| | | | | | | | | | routed to the Watchdog handler Patch by Eugene Surovegin, 18 Jun 2005
generated by cgit v1.1 at 2024-11-18 11:08:11 +0000