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* Big white-space cleanup.Wolfgang Denk2008-05-21-2/+2
| | | | | | | | | | | This commit gets rid of a huge amount of silly white-space issues. Especially, all sequences of SPACEs followed by TAB characters get removed (unless they appear in print statements). Also remove all embedded "vim:" and "vi:" statements which hide indentation problems. Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Add -mno-spe to e500/85xx buildsKumar Gala2008-04-29-0/+1
| | | | | | | | | | | Newer gcc's might be configured to enable autovectorization by default. If we happen to build with one of those compilers we will get SPE instructions in random code. -mno-spe disables the compiler for automatically generating SPE instructions without our knowledge. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx/86xx: Rename ext_refrec to timing_cfg_3 to match docsKumar Gala2008-04-29-2/+2
| | | | | | | All the 85xx and 86xx UM describe the register as timing_cfg_3 not as ext_refrec. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Additional fixes and cleanup of MP codeKumar Gala2008-04-29-2/+7
| | | | | | | | | | | | | | | | | * adjust __spin_table alignment to match ePAPR v0.94 spec * loop over all cpus when determing who is up. This fixes an issue if the "boot cpu" isn't core0. The "boot cpu" will already be in the cpu_up_mask so there is no harm * Added some protection in the code to ensure proper behavior. These changes are explicitly needed but don't hurt: - Added eieio to ensure the "hot word" of the table is written after all other table updates have occurred. - Added isync to ensure we don't prefetch loading of table entries until we a released These issues we raised by Dave Liu. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Round up frequency calculations to get reasonable outputKumar Gala2008-04-24-7/+6
| | | | | | | | | | | eg. because of rounding error we can get 799Mhz instead of 800Mhz. Introduced DIV_ROUND_UP and roundup taken from linux kernel. Signed-off-by: Dejan Minic <minic@freescale.com> Signed-off-by: Srikanth Srinivasan <srikanth.srinivasan@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Acked-by: Andy Fleming <afleming@freescale.com>
* 85xx: Fix size of cpu-release-addr propertyKumar Gala2008-04-18-1/+1
| | | | | The cpu-release-addr is defined as always being a 64-bit quanity regardless if we are running on a 32-bit or 64-bit machine.
* Fix calculation of I2C clock for some 85xx chipsTimur Tabi2008-04-18-1/+30
| | | | | | | | | | | Some 85xx chips use CCB as the base clock for the I2C. Some use CCB/2, and some use CCB/3. There is no pattern that can be used to determine which chips use which frequency, so the only way to determine is to look up the actual SOC designation and use the right value for that SOC. Update immap_85xx.h to include the GUTS PORDEVSR2 register. Signed-off-by: Timur Tabi <timur@freescale.com>
* 85xx: Fix detection of MP cpu spin upKumar Gala2008-04-11-1/+5
| | | | | | | | We were looking at the wrong memory offset to determine of a secondary cpu had been spun up or not. Also added a warning message if the all the secondary cpus we expect don't spin up. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use SVR_SOC_VER instead of SVR_VERKumar Gala2008-04-11-2/+2
| | | | | | | | The recent change introduced by 'Update SVR numbers to expand support' now requires that we use SVR_SOC_VER instead of SVR_VER if we want to compare against a particular processor id. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add cpu_mp_lmb_reserve helper to reserve boot pageKumar Gala2008-03-26-0/+15
| | | | | | | Provide a board_lmb_reserve helper function to ensure we reserve the page of memory we are using for the boot page translation code. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Update multicore boot mechanism to ePAPR v0.81 specKumar Gala2008-03-26-64/+115
| | | | | | | | | | | | The following changes are needed to be inline with ePAPR v0.81: * r4, r5 and now always set to 0 on boot release * r7 is used to pass the size of the initial map area (IMA) * EPAPR_MAGIC value changed for book-e processors * changes in the spin table layout * spin table supports a 64-bit physical release address Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix merge duplicationKumar Gala2008-03-26-49/+0
| | | | | | ft_fixup_cpu() got duplicated in some merge snafu. Remove the duplicate. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Speed up get_ddr_freq() and get_bus_freq()James Yang2008-03-26-16/+5
| | | | | | | | | | get_ddr_freq() and get_bus_freq() used get_sys_info() each time they were called. However, get_sys_info() recalculates extraneous information when called each time. Have get_ddr_freq() and get_bus_freq() return memoized values from global_data instead. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Show DDR memory data rate in addition to the memory clock frequency.James Yang2008-03-26-3/+6
| | | | | | | | | Show the DDR memory data rate in addition to the memory clock frequency. For DDR/DDR2 memories the memory data rate is 2x the memory clock. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: get_tbclk() speed up and rounding fixJames Yang2008-03-26-5/+3
| | | | | | | | | | Speed up get_tbclk() by referencing pre-computed bus clock frequency value from global data instead of sys_info_t. Fix rounding of result to nearest; previously it was rounding upwards. Signed-off-by: James Yang <James.Yang@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Update SVR numbers to expand supportAndy Fleming2008-03-26-37/+48
| | | | | | | | | | | | | FSL has taken to using SVR[16:23] as an SOC sub-version field. This is used to distinguish certain variants within an SOC family. To account for this, we add the SVR_SOC_VER() macro, and update the SVR_* constants to reflect the larger value. We also add SVR numbers for all of the current variants. Finally, to make things neater, rather than use an enormous switch statement to print out the CPU type, we create and array of SVR/name pairs (using a macro), and print out the CPU name that matches the SVR SOC version. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+49
| | | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: Added support for multicore boot mechanismKumar Gala2008-03-26-0/+405
| | | | | | | | | Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Add the concept of CFG_CCSRBAR_PHYSKumar Gala2008-03-26-3/+3
| | | | | | | | | When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Don't icbi when unlocking the cacheKumar Gala2008-02-27-5/+2
| | | | | | | | | There is no reason to icbi when invalidating the temporary stack in the d-cache. Its impossible on e500 to have the i-cache contain any addresses in the temp stack and it can be problematic in generating transactions on the bus to non-valid addresses. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Fix source for ECM error IVPRAndy Fleming2008-02-27-1/+1
| | | | | | | | The source vector for the ECM was being set to 2, but that's what the source vector for DDR was being set to. Change it to 1. Signed-off-by: Andy Fleming <afleming@freescale.com>
* Invalidate INIT_RAM TLB mappingsAndy Fleming2008-02-27-0/+11
| | | | | | | | | | | | | | | Commit 0db37dc... (and some others) changed the INIT_RAM TLB mappings to be unguarded. This collided with an existing "bug" where the mappings for the INIT_RAM were being kept around. This meant that speculative loads to those addresses were succeeding in the TLB, and going out to the bus, where they were causing an exception (there's nothing at that address). The Flash code was coincidentally causing such a speculative load. Rather than go back to mapping the INIT RAM as guarded, we fix it so that the entries for the INIT_RAM are invalidated. Thus the speculative loads will fail in the TLB, and have no effect. Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx, 86xx: Determine I2C clock frequencies and store in global_dataTimur Tabi2008-02-14-0/+3
| | | | | | | | | Update global_data to define i2c1_clk and i2c2_clk to 85xx and 86xx. Update the get_clocks() function in 85xx and 86xx to determine the I2C clock frequency and store it in gd->i2c1_clk and gd->i2c2_clk. Signed-off-by: Timur Tabi <timur@freescale.com>
* PPC: Use r2 instead of r29 as global data pointerWolfgang Denk2008-02-14-1/+2
| | | | | | | | | | | | R29 was an unlucky choice as with recent toolchains (gcc-4.2.x) gcc will refuse to use load/store multiple insns; instead, it issues a list of simple load/store instructions upon function entry and exit, resulting in bigger code size, which in turn makes the build for a few boards fail. Use r2 instead. Signed-off-by: Wolfgang Denk <wd@denx.de>
* ppc: Refactor cache routines, so there is only one common set.Rafal Jaworowski2008-02-14-45/+0
| | | | Signed-off-by: Rafal Jaworowski <raj@semihalf.com>
* QE: Move FDT support into a common fileKumar Gala2008-02-12-5/+3
| | | | | | | Move the flat device tree setup for QE related devices into a common file shared between 83xx & 85xx platforms that have QE's. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Coding Style Cleanup; update CHANGELOGWolfgang Denk2008-01-23-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Get ride of old TLB setup codeKumar Gala2008-01-17-22/+0
| | | | | | | Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Reworked initial processor initKumar Gala2008-01-17-72/+115
| | | | | | | | | | | | | | | | | | | Reworked the initial processor initialzation sequence: * introduced cpu_early_init_f that is run in address space 1 (AS=1) * Moved TLB/LAW and CCSR init into cpu_early_init_f() * Reworked initial asm code to do most of the core init before TLBs The main reasons for these changes are to allow handling of 36-bit phys addresses in the future and some of the issues that will exist when we do that. There are a few caveats on what can be initialized via the LAW and TLB static tables: * TLB entry 14/15 can't be initialized via the TLB table * any LAW that covers the implicit boot window (4G-8M to 4G) must map to the code that is currently executing. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Introduce new tlb APIKumar Gala2008-01-17-14/+99
| | | | | | | | | | Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Remove old style of LAW initKumar Gala2008-01-16-28/+0
| | | | | | All boards are now using the new fsl_law code so we can drop the old version. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Move LAW init code into CKumar Gala2008-01-16-0/+18
| | | | | | | | | | | Move the initialization of the LAWs into C code and provide an API to allow modification of LAWs after init. Board code is responsible to provide a law_table and num_law_entries. We should be able to use the same code on 86xx as well. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add QE brg freq and correct qe bus freq fdt update codeKim Phillips2008-01-09-1/+3
| | | | | Signed-off-by: Kim Phillips <kim.phillips@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
* 85xx: add ability to upload QE firmwareTimur Tabi2008-01-09-0/+1
| | | | | | | | | | | Define the layout of a binary blob that contains a QE firmware and instructions on how to upload it. Add function qe_upload_firmware() to parse the blob and perform the actual upload. Add command-line command "qe fw" to take a firmware blob in memory and upload it. Update ft_cpu_setup() on 85xx to create the 'firmware' device tree node if U-Boot has uploaded a firmware. Fully define 'struct rsp' in immap_qe.h to include the actual RISC Special Registers. Signed-off-by: Timur Tabi <timur@freescale.com>
* 85xx: Remove cache config from configs.hKumar Gala2008-01-09-2/+7
| | | | | | | | | Either use the standard defines in asm/cache.h or grab the information at runtime from the L1CFG SPR. Also, minor cleanup in cache.h to make the code a bit more readable. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Reworked FSL Book-E TLB macros to be more readableKumar Gala2008-01-09-13/+10
| | | | | | | | | | | The old macros made it difficult to know what WIMGE and perm bits were set for a TLB entry. Actually use the bit masks for these items since they are only a single bit. Also moved the macros into mmu.h out of e500.h since they aren't specific to e500. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Handle Asynchronous DDR clock on 85xxKumar Gala2007-12-11-4/+43
| | | | | | | | | | The MPC8572 introduces the concept of an asynchronous DDR clock with regards to the platform clock. Introduce get_ddr_freq() to report the DDR freq regardless of sync/async mode. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t on 85xxKumar Gala2007-12-11-32/+18
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_*_ADDR as the base of the registers instead of getting it via &immap. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Remove CONFIG_OF_FLAT_TREE related code from mpc85xx since we now use libfdtKumar Gala2007-12-11-123/+0
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t for cpm offset on 85xxKumar Gala2007-12-11-66/+63
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_CPM_ADDR as the base of the CPM registers instead of getting it via &immap->im_cpm. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Stop using immap_t for guts offset on 85xxKumar Gala2007-12-11-6/+5
| | | | | | | | In the future the offsets to various blocks may not be in same location. Move to using CFG_MPC85xx_GUTS_ADDR as the base of the guts registers instead of getting it via &immap->im_gur. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Add libfdt based ft_cpu_setup for mpc85xxKumar Gala2007-12-11-1/+67
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Cleanup coding style; update CHANGELOGWolfgang Denk2007-11-03-2/+2
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* Setting MSR[DE] in do_reseturwithsughosh@gmail.com2007-10-19-1/+6
| | | | | | | | Hello, This patch ensures the soft reset of the board for the 85xx boards by setting the MSR[DE] in the do_reset function. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
* MSR overwrite fixurwithsughosh@gmail.com2007-10-19-8/+3
| | | | | | | | Hello, This patch fixes the MSR overwrite in the start.S when moving out of the last 4K page. Signed-off-by: Sughosh Ganu <urwithsughosh@gmail.com>
* Remove magic numbers from cache related operations for mpc85xxKumar Gala2007-10-19-4/+4
| | | | | | | The mpc85xx start code uses some magic numbers that we actually have #defines for in <config.h> so use those instead. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx io out functions need sync after write.Ed Swarthout2007-09-26-0/+5
| | | | | | This fixes the mc146818 rtc_read/write functions for 85xx. Signed-off-by: Ed Swarthout <Ed.Swarthout@freescale.com>
* Enable L2 cache for MPC8568MDS boardHaiying Wang2007-08-29-1/+1
| | | | | | The L2 cache size is 512KB for 8568, print out the correct informaiton. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xxCDS: Add make targets for legacy systems.Randy Vinson2007-08-14-1/+1
| | | | | | | | The PCI ID select values on the Arcadia main board differ depending on the version of the hardware. The standard configuration supports Rev 3.1. The legacy target supports Rev 2.x. Signed-off-by Randy Vinson <rvinson@mvista.com>
* Add support for UEC to 8568Andy Fleming2007-08-14-2/+142
| | | | | Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com> Signed-off-by: Andy Fleming <afleming@freescale.com>
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