summaryrefslogtreecommitdiff
path: root/cpu/mpc85xx
Commit message (Expand)AuthorAgeLines
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-47/+27
* 85xx: Format cpu freq printing to handle 8 coresKumar Gala2009-02-16-3/+5
* Add secondary CPUs processor frequency for e500 coreHaiying Wang2009-01-23-8/+24
* 85xx: Convert CONFIG_SYS_PCI*_IO_BASE to _IO_BUS for FSL boardsKumar Gala2009-01-23-4/+12
* 85xx: Convert CONFIG_SYS_{PCI*,RIO*}_MEM_BASE to _MEM_BUS for FSL boardsKumar Gala2009-01-23-4/+12
* Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang2009-01-13-1/+5
* mpc8[56]xx: Put localbus clock in sysinfo and gdTrent Piepho2008-12-19-26/+32
* mpc8568: Double local bus clock dividerTrent Piepho2008-12-19-2/+2
* 85xx: Fix the boot window issueDave Liu2008-12-19-8/+8
* Set IVPR to kenrel entry point in second core boot pageHaiying Wang2008-12-19-0/+1
* mpc8xxx: LCRR[CLKDIV] is sometimes five bitsTrent Piepho2008-12-19-1/+1
* mpc8[56]xx: Put localbus clock in device treeTrent Piepho2008-12-19-1/+7
* 85xx: Add support to populate addr map based on TLB settingsKumar Gala2008-12-19-0/+34
* Update U-Boot's build timestamp on every compilePeter Tyser2008-12-06-1/+2
* 85xx: init gd as early as possibleKumar Gala2008-12-04-6/+6
* 85xx: Fix relocation of CCSRBARKumar Gala2008-12-04-4/+5
* 85xx: Add PORDEVSR_PCI1 definePeter Tyser2008-12-04-1/+1
* 85xx: Add CPU 2 errata workaround to all 8548 boardsPeter Tyser2008-12-03-0/+13
* Moved initialization of QE Ethernet controller to cpu_eth_init()Ben Warren2008-11-09-0/+18
* Moved initialization of FCC Ethernet controller to cpu_eth_initBen Warren2008-11-09-1/+4
* Fix typo in cpu/mpc85xx/cpu.cBen Warren2008-11-09-1/+1
* 85xx: Fix the incorrect register used for DDR erratum1Dave Liu2008-10-24-3/+6
* 85xx: Add basic e500mc core supportKumar Gala2008-10-24-0/+14
* 85xx: Use CONFIG_SYS_CACHELINE_SIZE instead of magic numberKumar Gala2008-10-24-2/+2
* Use strmhz() to format clock frequenciesWolfgang Denk2008-10-21-11/+15
* Merge 'next' branchWolfgang Denk2008-10-18-156/+221
|\
| * 85xx if NUM_CPUS>1, print cpu numberEd Swarthout2008-10-18-0/+5
| * Have u-boot pass stashing parameters into device treeAndy Fleming2008-10-18-0/+11
| * 85xx: Export invalidate_{i,d}cache and add flush_dcacheKumar Gala2008-10-18-0/+49
| * rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-156/+156
* | Revert "85xx: Using proper I2C source clock divider for MPC8544"Kumar Gala2008-10-17-2/+2
|/
* 85xx: Using proper I2C source clock divider for MPC8544Wolfgang Grandegger2008-10-08-2/+2
* Fix the incorrect DDR clk freq reporting on 8536DSJason Jin2008-10-07-2/+4
* 85xx: Remove setting of *cache-line-size in device treesKumar Gala2008-10-07-3/+0
* Fix printf errors under -DDEBUGAndrew Klossner2008-09-09-7/+7
* 85xx: Ensure timebase is zero on secondary coresKumar Gala2008-09-09-0/+5
* Removed hardcoded MxMR loop value from upmconfig() for MPC85xx.Sergei Poselenov2008-09-08-8/+7
* Pass in tsec_info struct through tsec_initializeAndy Fleming2008-09-02-23/+10
* mpc85xx: remove redudant code with lib_ppc/interrupts.cKumar Gala2008-08-27-97/+12
* mpc85xx: Add support for the MPC8536Kumar Gala2008-08-27-1/+199
* mpc85xx: Add support for the MPC8572DS reference boardKumar Gala2008-08-27-2/+2
* FSL DDR: Remove old SPD support from cpu/mpc85xxKumar Gala2008-08-27-1166/+0
* FSL DDR: Add 85xx specific register settingKumar Gala2008-08-27-0/+318
* FSL DDR: Add e500 TLB helper for DDR codeKumar Gala2008-08-27-0/+64
* FSL DDR: Rewrite the FSL mpc8xxx DDR controller setup code.Kumar Gala2008-08-27-1/+10
* fdt: rework fdt_fixup_ethernet() to use env instead of bd_tKumar Gala2008-08-21-1/+1
* 85xx: Rename CONFIG_NR_CPUS to CONFIG_NUM_CPUSKumar Gala2008-08-12-3/+3
* Merge branch 'master' of git://git.denx.de/u-boot-mpc85xxWolfgang Denk2008-07-15-23/+42
|\
| * 85xx: Cleanup L2 cache size detectionKumar Gala2008-07-14-17/+30
| * 8xxx-fdt: set ns16550 clock from CFG_NS16550_CLK, not bi_busfreqPaul Gortmaker2008-07-14-1/+1
generated by cgit v1.1 at 2024-11-19 15:02:32 +0000