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* ppc: Move cpu/$CPU to arch/ppc/cpu/$CPUPeter Tyser2010-04-13-277/+0
| | | | Signed-off-by: Peter Tyser <ptyser@xes-inc.com>
* ppc/85xx: Make SPD DDR TLB setup code use dynamic entry allocationKumar Gala2010-01-05-6/+6
| | | | | | | | Now that we track which TLB CAM entries are used we can allocate entries on the fly. Change the SPD DDR TLB setup code to assume we use at most 8 TLBs (or the number free, which ever is fewer). Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Add tracking of TLB CAM usageKumar Gala2010-01-05-0/+64
| | | | | | | | | We need to track which TLB CAM entries are used to allow us to "dynamically" allocate entries later in the code. For example the SPD DDR code today hard codes which TLB entries it uses. We can now make that pick entries that are free. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Fix how we determine the number of CAM entriesKumar Gala2009-11-13-2/+2
| | | | | | | | We were incorrectly use the max CAM size as the number of entries in the array for setting up the addrmap. We should be using the NENTRY field which is the low 12-bits of TLB1CFG. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: add boot from NAND/eSDHC/eSPI supportMingkai Hu2009-09-15-0/+2
| | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | | The MPC8536E is capable of booting form NAND/eSDHC/eSPI, this patch implements these three bootup methods in a unified way - all of these use the general cpu/mpc85xx/start.S, and load the main image to L2SRAM which lets us use the SPD to initialize the SDRAM. For all three bootup methods, the bootup process can be divided into two stages: the first stage will initialize the corresponding controller, configure the L2SRAM, then copy the second stage image to L2SRAM and jump to it. The second stage image is just like the general U-Boot image to configure all the hardware and boot up to U-Boot command line. When boot from NAND, the eLBC controller will first load the first stage image to internal 4K RAM buffer because it's also stored on the NAND flash. The first stage image, also call 4K NAND loader, will initialize the L2SRAM, load the second stage image to L2SRAM and jump to it. The 4K NAND loader's code comes from the corresponding nand_spl directory, along with the code twisted by CONFIG_NAND_SPL. When boot from eSDHC/eSPI, there's no such a first stage image because the CPU ROM code does the same work. It will initialize the L2SRAM according to the config addr/word pairs on the fixed address and initialize the eSDHC/eSPI controller, then load the second stage image to L2SRAM and jump to it. The macro CONFIG_SYS_RAMBOOT is used to control the code to produce the second stage image for all different bootup methods. It's set in the board config file when one of the bootup methods above is selected. Signed-off-by: Mingkai Hu <Mingkai.hu@freescale.com> Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Move code around to prep for NAND_SPLKumar Gala2009-09-15-23/+23
| | | | | | | | If we move some of the functions in tlb.c around we need less ifdefs. The first stage loader just needs invalidate_tlb and init_tlbs. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Repack tlb_table to save spaceKumar Gala2009-09-15-4/+5
| | | | | | | | We can pack the initial tlb_table in MAS register format and use write_tlb to set things up. This savings can be helpful for NAND style first stage boot loaders. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Introduce low level write_tlb functionKumar Gala2009-09-15-13/+3
| | | | | | | | | Factor out the code we use to actually write a tlb entry. set_tlb is a logical view of the TLB while write_tlb is a low level matching the MAS registers. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* ppc/85xx: Ensure that MAS8 is zero when writing TLB entries.Scott Wood2009-09-15-0/+3
| | | | | | | | Its reset value is random, and we sometimes read uninitialized TLB arrays. Make sure that we don't retain MAS8 from reading such an entry if the VF bit in MAS8 is set, attempts to use the mapping will trap. Signed-off-by: Scott Wood <scottwood@freescale.com>
* ppc/85xx: Add a simple function to search the TLBKumar Gala2009-09-08-0/+27
| | | | | | | | | | | Allow us to search the TLB array based on an address. This is useful if we want to change an entry but dont know where it happens to be located. For example, the boot page mapping we use on MP or the flash TLB that we change the WIMGE settings for after we've relocated. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Prepare 2009.08-rc3v2009.08-rc3Wolfgang Denk2009-08-22-1/+1
| | | | | | Update CHANGELOG, minor Coding Style cleanup. Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Fix addrmap to include memoryKumar Gala2009-08-14-6/+22
| | | | | | | | | | | | | | When we init the addrmap based on the TLB we will not end up getting the TLB that covers memory if we are using SPD. The reason is we haven't relocated at the point that we setup the memory TLB and thus it will not get setup in the addrmap. Instead we can just walk over the TLB array after we've relocated and see all the TLBs that have been set and use that information to populate the initial addrmap. By doing this we insure that we get the TLB entries that cover memory. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Use print_size to report amount of memory not mapped by TLBsKumar Gala2009-06-12-1/+1
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: bugfix for reading maximum TLB size on mpc85xxFredrik Arnerup2009-06-09-1/+1
| | | | | | | | | | | | | The MAXSIZE field in the TLB1CFG register is 4 bits, not 8 bits. This made setup_ddr_tlbs() try to set up a TLB larger than the e500 maximum (256 MB) which made u-boot hang in board_init_f() when trying to create a new stack in RAM. I have an mpc8540 with one 1GB dimm. Signed-off-by: Fredrik Arnerup <fredrik.arnerup@edgeware.tv> Signed-off-by: Andy Fleming <afleming@freescale.com> Acked-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Fix how we map DDR memoryKumar Gala2009-02-16-47/+27
| | | | | | | | | Previously we only allowed power-of-two memory sizes and didnt handle >2G of memory. Now we will map up to CONFIG_MAX_MEM_MAPPED and should properly handle any size that we can make in the TLBs we have available to us Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Change DDR tlb start entry to CONFIG param for 85xxHaiying Wang2009-01-13-1/+5
| | | | | | | So that we can locate the DDR tlb start entry to the value other than 8. By default, it is still 8. Signed-off-by: Haiying Wang <Haiying.Wang@freescale.com>
* 85xx: Add support to populate addr map based on TLB settingsKumar Gala2008-12-19-0/+34
| | | | Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* rename CFG_ macros to CONFIG_SYSJean-Christophe PLAGNIOL-VILLARD2008-10-18-1/+1
| | | | Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
* FSL DDR: Add e500 TLB helper for DDR codeKumar Gala2008-08-27-0/+64
| | | | | | | Provide a helper function that board code can call to map TLBs when setting up DDR. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* Coding Style Cleanup; update CHANGELOGWolfgang Denk2008-01-23-1/+0
| | | | Signed-off-by: Wolfgang Denk <wd@denx.de>
* 85xx: Get ride of old TLB setup codeKumar Gala2008-01-17-2/+0
| | | | | | | Now that all boards have been converted, remove old config code and the config option for the new style. Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
* 85xx: Introduce new tlb APIKumar Gala2008-01-17-0/+95
Add a set of functions to manipulate TLB entries: * set_tlb() - write a tlb entry * invalidate_tlb() - invalidate a tlb array * disable_tlb() - disable a variable size tlb entry * init_tlbs() - setup initial tlbs based on static table Signed-off-by: Kumar Gala <galak@kernel.crashing.org>
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